Outlook 2015: Differentiated FPGAs for a hyperconnected world

We have historically experienced that while every technological advancement brings fresh opportunities, it also creates an additional series of technological and infrastructure challenges that require a completely different set of innovative solutions. Intellectual property protection, security, cybercrime, eco-friendly standards and reliability are only some of the challenges that technology companies need to address. Technology companies developing products for the hyperconnected world typically rely on one of the following three fundamental design methodologies to incorporate required functionalities into one or more highly-integrated devices: Application specific standard products (ASSPs) are frequently an ideal solution for a new design. However, developers cannot always find an ASSP based solution that encompasses all the required functions for a new design on one device. Additionally, companies that are designing the latest ASSPs are interested mostly in very high volume applications to amortise the extremely high development cost. This leaves many applications without a 'so called' off the shelf ASSP solution. Application specific integrated circuits (ASICs) have traditionally been excellent solutions for companies that had the goal of integrating their system requirements in a single device. As our industry moved toward smaller geometries, ASIC related challenges, such as the overall design cycle time and its enormous associated costs (including EDA tools) have prevented more and more designers from using ASICs, forcing them to look for other methodologies to solve their complex design and integration challenges. Field programmable gate arrays (FPGAs) have come a long way in the past two decades with regard to integration capabilities, size, built-in functions such complex I/Os, memories, CPUs and DSPs. FPGAs are the fastest way to integrate a specific design into one device. The cost of FPGAs is traditionally higher than ASSPs or traditional ASICs, but they provide huge advantages in supporting and facilitating field upgradability, design flexibility and faster time to market. Today, FPGAs provide an outstanding solution for system architects and promise a significantly better overall total cost of ownership (TCO) in many next-generation designs, compared to ASICs. Technology companies developing new products are frequently selecting FPGAs to meet their challenging and stringent design constraints. This is a significant shift and an enormous advantage for the handful of companies developing complex FPGA solutions. Current solutions from the major FPGA suppliers boast excellent innovation, with advanced built-in functions such as math blocks, high speed serial interfaces, embedded memories and various CPU/DSP cores once only available in ASIC based component designs. Predictions for the FPGA market show that system architects designing complex products for the hyperconnected world will continue to require unique built-in features and differentiated capabilities for emerging applications in communications, industrial, medical and defence. This places additional demands for even higher security capabilities, low overall power consumption, significantly improved reliability and application specific system integration targeted to the end user. Not all FPGA vendors have addressed all of these rigorous challenges in a 'single device'. An FPGA provider that can deliver security, low power, reliability and high level of integration in a single device provides the system architect with the best solution. The key features that bring significant product differentiations to end users in a hyperconnected world are security, low power, high reliability and system integration. Security Today's complex FPGA designs contain many advanced IPs and, in our hyperconnected world, it is essential that all FPGAs be protected from being cloned, reverse engineered or tampered with in order to protect these embedded IPs. FPGAs also need to become the root of trust in complex applications. The greatest advances in device security come from making base level security easy to use and adopt. The ideal solution is to provide FPGAs with leading edge embedded security technology that works inherently. One of the issues with SRAM based FPGAs is the need to configure the device from an external memory device every time it is turned on. This vulnerability exposes the design to reverse engineering. By storing the configuration information in non volatile on chip memory, it becomes impossible to capture the information and also prevents reverse engineering and tampering with the design for malicious effect. Current generations of FPGAs only provide design security. It is necessary for advanced security features to go beyond the norm to address data security and to protect the application data that the FPGA is processing. Examples of the data security features necessary for new applications in our hyperconnected world include: • hardware protection from differential power analysis (DPA) attacks • non-deterministic random bit (number) generator • hardware firewalls to protect the integrated ARM Cortex-M3 MCU core Low power In the last two decades, many advanced CPUs and MCUs have architected various power saving modes to address the power consumption issues caused by higher frequencies and higher integration. Only the most advanced FPGAs have been architected properly to provide similar advanced low power capabilities while offering higher frequency devices. Customers now have access to low power modes implemented in non volatile memory based FPGAs for the first time. High reliability Many commercial aviation, military systems and space vehicles are required to meet strict size weight and power (SWaP) targets and to meet operational product life objectives. Military systems must operate flawlessly after, and often over, prolonged periods of storage. Meanwhile, industrial systems are increasingly required to meet safety standards before they can be delivered to end equipment users, while the need for the highest-reliability in medical systems has always been a focus area. Reliability issues in FPGAs are mostly caused by single event upsets (SEU) changing the contents of the configuration SRAM. Because the SRAM controls the routing and logic configuration of the device, any change will cause an error in the design. This is an issue that is largely ignored or even hidden from the customers by vendors of SRAM based FPGAs. Flash memory based FPGAs are immune to the effects of an SEU, eliminating the possibility of design corruption and removing the most common failure mode from a system. They also remove the need for SEU mitigation found in some SRAM based FPGAs. System integration Integration of an embedded processor core removes the need for a soft processor core to be created in the FPGA fabric and negates the speed and size penalties of this approach. The same is true of tightly coupling peripherals and subsystems, such as memory controllers, analogue blocks, DSPs, and high-speed I/Os. With non-volatile FPGAs, designers do not need separate memory to hold the device configuration. Integrating FPGAs with other components, such as microprocessors, memory devices and DDR memory interfaces, reduces the component count on a board and improves the overall system reliability. The future To ensure the viability of projects that cater to the hyperconnected world, major advancements and differentiation in FPGA technology in these areas will be critical during the coming decade: security; low power; reliability; and system-level integration. Microsemi Microsemi Corporation offers a comprehensive portfolio of semiconductor and system solutions for communications, defence and security, aerospace and industrial markets. Products include high-performance and radiation-hardened analogue mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronisation devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 3,400 employees globally. Paul Pickle is president and chief operating officer of Microsemi.