The devices are intended to ensure data reliability in a wide variety of industrial, military, communication, data processing, medical, consumer and automotive applications.
Soft errors caused by background radiation can corrupt memory content, resulting in a loss of critical data. A hardware ECC block in the new asynchronous SRAM family is able to perform all error correction functions inline, without user intervention, and as a result deliver Soft Error Rate (SER) performance of less than 0.1 FIT/Mb (one FIT is equivalent to one error per billion hours of device operation).
The new devices are pin-compatible with current asynchronous fast and low-power SRAMs, enabling customers to raise system reliability while retaining board layout. The 4Mb SRAMs also include an optional error indication signal that indicates the correction of single-bit errors.
Theses new SRAMs are available in three options: Fast, MoBL and Fast with PowerSnooze, an additional power-saving Deep Sleep mode that achieves 15 uA (max) deep-sleep current for the 4Mb SRAM.
Each of the options is offered in industry standard x8 and x16 configurations and the devices operate at multiple voltages (1.8V, 3V, and 5V) over -40°C to 85°C (Industrial) and -40°C to 125°C (Automotive-E) temperature ranges.
