According to the company, Libero SoC tool suite includes the Mentor Graphics ModelSim Simulator allowing line by line verification of hardware description language code. Simulation can be performed at all levels: behavioural (pre-synthesis), structural (post-synthesis), and back-annotated, dynamic simulation.
A graphical user interface enables quick identification and debug of problems. Libero SoC v11.8 now includes ModelSim Microsemi Pro, allowing customers to simulate in mixed language environments.
While breakpoints have been used historically in embedded software, they can now be used to support FPGA logic debug functions. These SmartDebug enhancements complement existing debug capabilities which offer a new approach to debug FPGA devices’ status, memory and Serialiser/Deserialiser (SerDes) transceivers without using an integrated logic analyser.
The Libero SoC is suitable for FPGA designs targeting applications within the aerospace, defence, security, communications, data centres, industrial and automotive markets.
Additional features include a netlist viewer providing visibility into different internal structures, constraints management features offering block flow and an input/output (I/O) advisor, 20% runtime improvements for its SmartTime user interface and Windows 10 operating system support.
To facilitate broad adoption, Libero SoC v11.8 also comes with a new 60 day evaluation license which can be used to evaluate Microsemi flash-based FPGA and SoC reference designs, tutorials and application notes.
The software also features the company’s Secured Production Programming Solution, which generates and injects cryptographic keys and configuration bit streams to prevent overbuilding, cloning, reverse engineering, malware insertion and other security threats.
