In a PQFN 3.3 x 3.3 mm 2 package and with a wide voltage class ranging from 25 V up to 100 V this package, according to Infineon, sets a new standard in power MOSFET performance, offering higher efficiency, higher power density, superior thermal management and low bill-of-material (BOM). The PQFN addresses applications including motor drives, SMPS for server and telecom and OR-ing, as well as battery management systems.
This Source-Down package technology enables a larger silicon die in the same package outline. In addition, the losses contributed by the package, limiting the overall performance of the device, can be reduced. This enables a reduction in R DS(on) by up to 30 percent compared to the state of the art Drain-Down package. The benefit at the system level is a shrink in the form factor with the possibility to move from a SuperSO8 5 x 6 mm 2 footprint to a PQFN 3.3 x 3.3 mm 2 package with a space reduction of about 65 percent and allowing available space to be used more effectively, enhancing the power density and system efficiency in the end system.
In addition, with the Source-Down concept, the heat is dissipated directly into the PCB through a thermal pad instead of over the bond wire or the copper clip. This improves the thermal resistance R thJC by more than 20 percent, from 1.8 K/W down to 1.4 K/W, enabling simplified thermal management.
Infineon is offering two different footprint versions and layout options: the SD Standard-Gate and the SD Center-Gate. The Standard-Gate layout simplifies the drop-in replacement of Drain-Down packages, while the Center-Gate layout enables optimised and easier parallelization.
These two options can bring optimal device arrangement in the PCB, optimised PCB parasitics, and ease of use.
These OptiMOS power MOSFETs are now available in PQFN 3.3 x 3.3 mm 2 packaging, a wide range of voltage classes from 25 up to 100 V, and two different footprint versions.
