Lithography the biggest roadblock to Moore’s Law

The problem would not be so bad if lithography did not already dominate the cost equation. The machines used to define on-chip features have become progressively more expensive. Ten years ago, it was unthinkable that a scanner would cost much more than $10million; now, a price tag approaching $100m does not seem unrealistic. At the same time, their size and weight have ballooned – and weight turns out to be a surprisingly good indicator of scanner cost, something to consider when companies such as ASML talk about the cost of deploying extreme ultraviolet (EUV) equipment, one of the options under consideration. IMEC had to build a fab with a higher ceiling to accommodate the gigantic ASML-built EUV scanner the research institute would use to perform process development. Like an iceberg, much of a completed EUV scanner has to sit below the clean room in the sub-fab – and this includes an optics assembly that would not look out of place on a Death Star. However, if a scanner can work its way through enough wafers per hour, its price tag is not a problem for big chipmakers, who do not have that much of an issue in financing an advanced fab. Unfortunately, throughput is where things begin to fall down in the economics of lithography. One $50m scanner will depreciate at approximately $1000 per hour, assuming it takes five years to write off the machine's value. During each hour, a scanner should work through at least 100 wafers. So, each time a wafer passes through the machine, it gets $10 added to its cost, even before you include the cost of the materials or the energy needed to power the scanner. While that doesn't sound too bad, a typical chip needs to go through a scanner or stepper at least 40 times. The good news is that not all the masks need the most expensive scanners. The upper, comparatively coarse, metal layers with a pitch of 0.5µm or more can be constructed with an i-line stepper – considered state of the art in the early 1990s. The depreciation on this much cheaper equipment is nowhere near as large. The bad news is that many of the most sensitive processes that demand multiple mask steps are in the lower layers. And the density requirements of a process such as 20nm demand the two lowest metal layers, and the vias that connect them together and to the polysilicon and substrate levels, need to be at the aggressive pitch of around 65nm, which is less than the resolution of an optical scanner, even one using highly advanced optical proximity correction and computational lithography (NE, 10 May 2011) techniques to extended the reach of 193nm optical lithography to the 28nm node. The industry needs something new. In principle, the best option on paper is extreme EUV. Unfortunately, the tools that would satisfy chipmakers' demands on cost only exist on paper. Today's experimental tools can only manage a maximum of 11 wafers per hour, increasing that cost per mask layer from $10 to almost $100. ASML promises that it will crack the 80 per hour mark by the end of the year, even though the cause for the low throughput has dogged EUV for years. However, the tools are likely to be almost twice as expensive as today's optical scanners, which will raise cost even further, unless the throughput issue is addressed. With a wavelength close to that of X-rays, the photons are not entirely straightforward to generate. The most practical approach heats tin into a very high-temperature plasma – when the electrons in that plasma re-associate with the tin ions, they emit photons with a wavelength of 13.5nm. The trouble is in generating emissions intense enough to expose an image on the surface of the wafer. At first glance, the power requirement does not seem to be too troublesome. To achieve a throughput of 100 wafers an hour, the light power has to be in the range of 200W, but the energy needed to produce light at this intensity is orders of magnitude higher. And it is still not clear what that source might be. Until a couple of years ago, laser-produced plasma (LPP) seemed to offer the greatest chance of success. This trains a powerful carbon dioxide laser – one that can cut through metal – on droplets of molten tin dropped into a vacuum chamber, evaporating the metal into a plasma. To achieve the tens of watts that an LPP source can produce today requires of the order of 40kW. The phenomenal energy demand worries foundries such as TSMC because of the extra cost it implies. Companies such as Cymer and Gigaphoton are confident they can increase efficiency and output, but are at the stage where they need to improve both by an order of magnitude in less than a year, having taken years to get to this point. The question over LPP source power has reopened the door for a technology that had been written off for a while because it showed little realistic prospect of achieving the necessary output power: discharge-produced plasma. However, by using laser-assisted discharges with a much smaller laser than with LPP, former Philips Electronics subsidiary Xtreme Technologies believes it can deliver the necessary power for less energy input. Xtreme's approach uses a lower-energy laser to vaporise tin from two spinning wheels (see fig 1), with the excitation energy provided by a 20kA current passing across the gap between the wheels. The resistance of the veil of gaseous tin between the spinning wheels raises the temperature high enough to form a plasma that can discharge significant numbers of 13.5nm photons – although this amount is still a long way from the 200W target. The company claims it can convert more than 2% of the power supplied to the discharge chamber. The source currently weighs 8tonne when fully assembled. Even when it has been generated, such short wavelength light is not easily handled. EUV photons cannot be steered by transmissive lenses: any focusing has to be done by reflective elements and the mask itself is reflective. Areas that are not meant to be printed scatter the light, rather than reflect it. Because of the risk of waiting for EUV to become cost-effective – if it ever does – most chipmakers have opted for double patterning at 20nm, and potentially beyond, despite the dramatic effect it will have on cost (NE, 26 July 2011). Instead of paying $10 per layer for the tool's depreciation, it will now cost $20, because you either halve throughput or buy twice as many scanners to cope with the critical layers. You also double the number of critical masks – which are not cheap themselves, especially if you are not dealing with massive volumes. This sudden jump is why 20nm wafers could cost 70% more than their 28nm equivalents. The biggest problem is not in printing small features, but in printing very closely spaced features. Double patterning works because it puts more space between features on each mask. However, there are a number of ways to put it into practice. The two techniques currently on the table are a chemically assisted form, called self aligned double patterning (SADP, see fig 2) and one that is likely to be mainstream at 20nm: pitch split or litho-etch, litho-etch (LELE, see fig 3). LELE is the easiest to understand: it simply involves splitting a design into two independent masks that are used to expose and etch away a resist pattern in two separate steps. As long as the masks overlay accurately, the result is a layout twice as dense as would be possible using a single exposure. In practice, there are offset errors and etching tolerances that will affect device behaviour. For this reason, EDA companies such as Cadence Design Systems recommend high-performance circuits go on the same layer, even if this means interleaving those paths with other logic defined on the other mask to avoid losing density. SADP, meanwhile, had its conceptual origins in interference-assisted double patterning. Although it demanded a big shift in design, Intel was able to deploy it successfully in its 45nm process, pointing the way to so-called 1D design. Recognising that diffraction gratings tend to be easily printed, the technique restricts the features that are defined on each layer to regularly spaced lines. A second mask, which does not require the same density of features, is used to select parts of those lines that need to be etched away to form isolated features. The result is a very dense pattern of cut lines that can then be connected using vias to orthogonally wired layers to form circuits. Struggling at 30nm Using conventional lithography, interference-assisted lithography starts to struggle at around 30nm. However, it is possible to give it a boost by using the self-alignment techniques that chipmakers have used for years to put sidewalls around the gate of a transistor. The chemical processes are designed such that walls only form alongside a previously defined gate. In SADP, the mask defines lines of resist along which sidewalls are chemically formed. The resist is then etched away, leaving two thin parallel lines separated by a gap. A cut mask then chops the lines up ready for interconnection. SADP is conceptually more difficult to deal with and is not popular amongst logic designers because it is hard to map metal layouts onto the two masks, although Intel demonstrated that 1D design was feasible and this has been embraced by some foundries, such as TSMC. It is potentially the most future-proof option, especially if EUV fails to take off, because you can extend it. In principle, it is possible to use further rounds of deposition and etching to form even more finely spaced pairs. Ultimately, SADP could lead to the use of bottom-up self-assembly techniques. Applied Materials, for example, has demonstrated the use of block copolymers that self align around mask-defined features and which, potentially, could define layouts – albeit using a highly restricted set of shapes – that have spacings of 10nm or less. Double patterning is not a very attractive option but, whatever happens at 20nm, it is likely to be the technique of choice by the end of the decade, even if EUV becomes mainstream. It may even be the means by which a lithographic wild card gets its foot in the door in the attempt to cut chipmaking costs. Startup Multibeam is working on the basis that SADP could be made a lot cheaper than other approaches by combining the chemically assisted line-definition stage with direct-write electron-beam scanners. The idea is that conventional optical lithography would define the grating-like array of lines that are then doubled-up chemically. Multibeam's e-beam tool would then define where the cuts are made in those lines. The advantage of using e-beam is that it can define much smaller features than is possible using optical lithography. The downside of e-beam is that it is woefully slow – worse even than an experimental EUV tool. The pattern is defined not by a mask, but by laboriously drawing it using a steerable beam. Even with advanced computer control, you would be lucky to get one wafer per hour out of a conventional e-beam tool. As a result, the machines are used to create masks, rather than chips. But two things are coming together that will help throughput. One is microelectromechanical machine (MEMS) technology, which makes it possible to steer not just one e-beam, but tens of thousands of them at once. The second is relative size. It should be possible to put ten e-beam tools into the same volume as a 193nm optical scanner with the wafers distributed among tools in the cluster according to availability. Extension to quad patterning would help the economics of Multibeam's approach because, as long as the lines need to be equally spaced, you only need one mask step, followed by a number of cheaper chemical operations. While Multibeam sees e-beam co-operating with existing scanner technologies, Mapper Technologies plans to use e-beam alone to define entire layers on the basis that a single exposure using e-beam could be cheaper overall even after the cost of clustering is taken into account. The key lies in moving from being able to deploy hundreds of e-beams at once to tens of thousands in a production tool. We have been here before. A number of lithography options were on the table in the mid-1990s: the last time optical seemed to be running out of steam. Names such as PREVAIL and SCALPEL are now just part of history, rather than being the future. And the same could yet happen to EUV and e-beam. Although the cost implications of double patterning are not pretty, they come with a lower risk. However, a secondary factor may come into play in determining whether optical lithography – with chemical assistance – can continue to serve. That is line-edge roughness. This major source of variability is hovering around the 10% level. If this gets worse, and there is every chance it will with optical, then chipmakers may be forced to switch horses, even if e-beam and EUV are not achieving their target throughputs. Variability affects yield and without good yield, as with low-throughput lithography, the economics of chipmaking go south very fast indeed.