Delays in EUV development threaten viability of lithographical approach

At a panel session at the VLSI Technology Symposium in Honolulu, Intel's director of lithography Yan Borodovsky argued that, by using the company's 1d approach to laying out critical layers of a chip, it was feasible to use chemical techniques to draw multiple parallel lines based on templates laid down by a conventional 193nm optical scanner. The primary use for EUV, if it arrives, would be for 'cut masks'; devices that modify the regular lines created by pitch splitting – Intel's term for multiple patterning. Cut masks are the most difficult to expose using 193nm equipment. Although EUV scanners are capable of producing production-ready wafers, throughput remains its Achilles Heel and, with it, cost. Burn Lin, vice president of R&D at TSMC, said the company's current EUV scanner has a throughput of just seven wafers per hour, rather than the 50 per hour that ASML said would be achievable at the end of 2011. The latter figure is the minimum level that is considered commercially viable. Lin argued that clusters of multiple electron beam direct write machines could substitute more cost effectively for EUV. Harry Levinson, senior fellow and manager of strategic litho at GlobalFoundries, said it could take until 2018 for the throughput of EUV to be high enough to be economically viable. Levinson said a likely scenario for the future is that multiple patterning would be replaced by directed self assembly, as that approach allows more complex structures to be formed, based on a template mask. "Cut masks will remain a challenge without EUV: in the future, I see a combination of directed self assembly and EUV, or maybe multibeam direct write for cuts," he said.