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Risc v

SEGGER announces support for Nuclei RISC-V processors

SEGGER releases Floating-Point Library to support RISC-V

SiFive and CEVA to bring ML processors to mainstream markets

Wind River announces RISC-V support for VxWorks RTOS

IAR Systems updates RISC-V development tools

Outlook 2020 - A shift in architectures is coming but it may not play out like the previous processor revolutions

UltraSoC and Europractice aim to help academic institutions develop full RISC-V ASICs

SEGGER SystemView for RISC-V now available

Intensivate uses SiFive's RISC-V to develop accelerator

IAR Systems updates RISC-V development tools

GigaDevice unveils 32bit general purpose microcontroller

Alibaba unveils16-core RISC-V chip