It’s a hard life for DSP functionality in FPGAs

But even though DSP functionality is available in FPGAs – all leading manufacturers provide a lot of DSP capability – taking advantage of that functionality has remained a challenge. In particular, translation from the floating point environment used in the development phase to the fixed point environment often required in production devices has been troublesome, to say the least. You hear stories about that taking 12 months; maybe longer than the shelf life of the product in which it features. Altera appears to have removed a lot of the pain by integrating hardened IEEE754 compliant floating point operators into its Arria 10 and Stratix 10 devices manufactured on TSMC's 20nm process. And the parts are currently shipping, with the necessary design tools to take advantage of the functionality. The key word here is 'hardened'. This isn't just an allocation of logic elements to DSP functionality; it's essentially inclusion on the die of asic like areas dedicated to DSP. It's something that's been appearing in Altera's FPGAs for a while now, technology inherited from its old HardCopy operation, which created ASIC like versions of FPGAs for cost sensitive applications. Strange how, at an increasing pace, FPGAs are becoming more like the ASICs to which they have always tried to provide an alternative.