Altera builds hardened DSP blocks into Arria and Stratix at 20nm
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Responding to the increasingly demanding task of designing floating point DSP capability into FPGAs, Altera has integrated IEEE754 compliant, floating point operators into Arria 10 and Stratix 10 devices manufactured on TSMC's 20nm process and currently shipping.
The move is said by the company to deliver 'unparalleled levels of DSP performance, designer productivity and logic efficiency' and to save 'up to 12 months of development time'.
By integrating hardened DSP blocks, used alongside an advanced tool flow, the devices can be used to address applications such as high performance computing (HPC), radar, scientific and medical imaging.
"The implementation of floating point DSP blocks in our devices is truly a game changer for FPGAs," claimed Alex Grbic, Altera's director of software, IP and DSP marketing. "With hardened floating point, Altera FPGAs and SoCs offer a performance and power efficiency advantage over microprocessors and GPUs in an expanded range of applications."
The blocks are said to allow Arria 10 devices to deliver up to 1.5TFLOPs and Stratix 10 parts to offer up to 10TFLOPs of DSP performance. DSP designers can choose either fixed or floating point modes, with the floating point blocks said to be backwards compatible with existing designs. DSP designs can also be translated directly into floating point hardware, rather than being converted into fixed point.
