Engineering publications brought to you by Mark Allen

EDA & Design Software

Codasip adds Veridify secure boot to RISC-V processors

Siemens’ NX delivers greater cross-discipline collaboration and knowledge capture

Codasip Studio Mac extends potential to design for differentiation with RISC-V

Synopsys gives a boost to 5G SoC development with new RF design flow

QuickLogic and eTopus develop flexible eFPGA chiplet template

Alchip Technologies offering 3nm ASIC design services

Siemens extends support of multiple IC design solutions for TSMC’s latest processes

Avery Design Systems announces verification support for new UCIe standard

Cadence Design IP portfolio in TSMC’s N5 Process gains broad adoption

SkyWater announces availability of 90nm SRAM memory compiler

OpenLight launches silicon photonics technology platform

Cadence accelerates SoC verification with expanded VIP and System VIP portfolio