The library is available in thick-oxide based cells, operating above the core voltage domain, minimising leakage and allowing easy migration across different process nodes even in FINFET technologies.
Commenting Barry Paterson, Agile Analog’s CEO, said, “The Agile DSCL has been developed to enable our customers to embed digital functionality within the analogue domain. These digital cells will operate within the analogue voltage domain which avoids excessive level shifting to the core domain and enables digital control to be tightly coupled to analogue IP.
“The DSCL has been developed to be process agnostic and therefore is available in the same processes as our analogue IP. The library fully supports industry standard digital design methodologies by making all required views available. Our Analog Digital Cell Library is already being used successfully in customer designs to support low power, always-on solutions for applications such as IoT.”
The DSCL IP blocks can be optimised for low-power, ultra-low leakage, high density or high-speed applications. There are also options for channel length and various track heights to provide flexibility for designers.
For specific design targets such as low-power designs, there is a special Power Management library.
The library can be optimised for other PPA targets to ensure that customers have the best solution for their application. It is also possible to generate models at customised PVT corners. The library has class-leading verification and is DFM-optimised.
Traditionally, analogue IP blocks have to be manually redesigned for each application and process technology, but Agile Analog has developed a unique way to automatically generate analogue IP to exactly meet the customer’s specifications and process technology.
Called Composa, it uses tried and tested analogue IP circuits that are in the company’s Composa library. Effectively, the design-once-and-re-use-many-times model of digital IP now applies to analogue IP for the first time.
As the analogue IP circuits in the Composa library have been extensively tested and used in previous designs, and are fully validated every time they are generated, this provides a similar level of reassurance to the digital IP world’s ‘silicon-proven’.
All the major foundries are supported including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and manufacturers.
