Breaking down barriers

The test challenges posed by disappearing pin access and increasing packaging densities are nothing new. The Joint Test Action Group (Jtag) responded to these challenges in the early 1990s with the introduction of the boundary scan methodology. Since then, awareness of the IEEE1149.1 boundary scan standard has grown, many semiconductors are boundary scan enabled and many embedded systems have a Jtag test access port (TAP). IEEE1149.1 defines the TAP, which consists of two supplementary pins for control and one each for input and output serial test data, and the boundary scan architecture. The additional circuitry forms a four wire serial communication bus. Independent of device function, this circuitry enables a snapshot of the logic state of all pins on the device to be captured and transmitted to the TAP. On a pcb, multiple boundary scan enabled chips can be daisy chained via their Jtag lines, giving engineers access to all devices through one probe connection. Logical fault finding techniques can then be used to track problems. Although envisaged primarily for board test in a manufacturing setting, embedded systems designers have capitalised on the access the boundary scan chain provides to the system. Programmers can, for example, use an in circuit emulator to access a microprocessor’s on chip debug module, then debug embedded system software and program cplds and flash devices.