In an RF system, the RF block interfaces with the antenna, and down-converts the RF signal to a baseband analogue signal. This article focuses on the analogue front end (AFE) block.
The AFE block is the critical bridge connecting RF sensor signal output to a digital application processor. However, ensuring the AFE block delivers the performance and low power required by the end application can be a formidable task.
Wireless system designers are increasingly adopting the IEEE802.11ac/d and Long-Term Evolution-Advanced (LTE-A) standards. IEEE802.11ac/d, the fifth generation WLAN standard, supports data rates of up to 6.93Gbit/s. LTE-A, meanwhile, is the fourth generation wireless communication standard. Its maximum channel bandwidth is 20MHz, and it uses techniques like OFDM and MIMO to achieve peak data rates of 300Mbit/s.
As protocols mature, there comes a point when there is consensus for system partitioning between the RF and AFE modules in order to support the latest standards.
Currently, there is a fair amount of consensus for optimal partitioning for both IEEE802.11a/b/g/n and LTE. Now, system optimisation techniques are focused on IEEE802.11ac/d and LTE-A.
RF systems: getting started
When defining an RF system, the system architect will typically start with the protocols they wish to target, after which the designer can determine the AFE's specifications.
The bandwidth of the baseband signal plays a primary role in determining the A/D converter's sampling rate. According to Nyquist, the A/D's sample rate should be more than twice the bandwidth of the baseband signal, in order to avoid any information loss during sampling. Other important factors include receiver sensitivity, adjacent channel rejection and noise figure.
The A/D typically consumes most of the power in the AFE's receive path. Faster sample speeds mean higher bandwidth and even more power consumption. Since low power consumption and long battery life are important for mobile devices, it's important to select an A/D with the lowest power consumption for the given specifications.
Two key data converter architectures have emerged: pipeline; and successive approximation register (SAR).
Comparing the two
The pipeline architecture provides a multistage conversion system. Each stage quantises the amplified quantisation error signal from the previous stage, which facilitates higher throughput. However, this architecture requires many precision analogue building blocks, which increases power consumption at advanced nodes.
The SAR architecture was generally believed to not support higher speeds and resolution because increases in resolution also increase exponentially the size of the D/A converter capacitor array. Exploiting digital friendly advanced process nodes has brought enhancements to the architecture. Today, it is possible to optimize area for higher resolution and, at advanced process nodes, the SAR architecture arguably offers the best speed:power ratio for A/Ds.
Why SAR is ideal
A SAR A/D consists of SAR logic, a comparator and a D/A converter, with a binary search algorithm at its foundation
In a traditional SAR A/D, the input is fed to a sample/hold circuit, which samples the input voltage and makes sure inputs to the comparator remain constant during the comparison phase, even if there are changes to the input voltage. A sample and hold amplifier (SHA) is usually implemented through a capacitor D/A.
While it used to be considered optional, an input buffer has now become a regular A/D component. This eliminates kick-back from the AFE block to the RF section by ensuring high impedance to the RF block and low impedance to the A/D. It can also be used to set the A/D's common mode, regardless of the common mode voltage of RF block output. This enables interfacing of the I/O voltage supplied RF block to the core voltage supplied A/D. The input buffer also simplifies the design of the RF output buffer because it drives the drain of the switches, which offers varying capacitive load. The RF output buffer drives a DC load only.
Often, in a high speed SAR A/D, the input buffer consumes as much power as the A/D's core. That's why it's important to compare 'complete' A/Ds and not just the core. The ideal situation is to optimise the A/D core and input buffer by budgeting the power between the two. With this approach, you can achieve low power and high speed performance.
As an example, consider a 12bit, 160Msample/s A/D which converts an analogue input in 6.25ns. The input to the A/D's core has to be settled to better than the A/D's accuracy – 12 bits just before the input is sampled. If the conversion time is 5ns, the input buffer will have to settle its output in 1.25ns. This requires an ultra fast input buffer – which would consume a substantial amount of power.
To effectively minimise power consumption in an AFE, we propose implementing an integrated architecture with optimised data converters and companion phase locked loops (PLLs). The PLLs should have extremely low accumulation jitter in order to deliver a high level of A/D performance. The number of IQ A/Ds should be configurable to exploit smart antenna technology (for example, MIMO and spatial diversity features) and meet a particular wireless standard. The A/D should also be designed with a SAR architecture.
Another key component is analogue/mixed signal IP cores that are customised and tested for wireless applications. For IP providers striving to meet wireless systems designer needs, the perceived Holy Grail has been to develop a universal, single-chip AFE that meets multiple wireless baseband requirements. However, this requires deep system level knowledge in order to specify, design and configure the wireless AFE. Technically, it's quite challenging because RF and digital requirements are different.
While scaling on the digital side is fairly easy, this isn't the case on the noise and leakage sensitive analogue side. Instead, IP providers would be well served to consider a modular approach to IP configuration, based on different yet complementary IP cores. With this approach, it's much easier for designers to integrate a versatile system that caters to multiple protocols.
For wireless systems designers, silicon proven IP cores can help overcome some of the challenges and complexities of designing analogue circuitry and also shorten the development cycle.
Madhusudan Govindarajan, principal design engineer, and Priyank Shukla, principal application engineer, are with Cadence's IP Group.
Analogue IP cores for integration into SoCs
Cadence has more than 250 silicon proven, hardened analogue IP cores in its portfolio, including AFEs, A/Ds and D/As, that can be integrated into a range of SoCs. The newest data converter IP are suited to 28nm designs, providing faster conversion rates while consuming less power and requiring less silicon area. The cores, based on a parallel SAR architecture, support next generation applications, including WiGig, and the latest wireless standards, including IEEE802.11ac/d. These solutions include:
• 12bit 80/160/320Msample/s A/D converter
• 12bit 240Msample/s D/A converter
• 7bit 3Gsample/s dual A/D and D/A converters
• 11bit 1.5Gsample/s dual A/D converter
• 12bit 2Gsample/s dual D/A converter
