They have four main elements: the sample and hold amplifier (SHA); an analogue comparator; a reference D/A converter; and the successive approximation register (SAR). Because the SAR controls the operation, they are often called SAR converters (see fig 1).
After power up and initialisation, a signal starts the conversion cycle. The switch closes, connecting the analogue input to the SHA, which acquires the input voltage. When the switch opens, the comparator determines whether the analogue input – now stored on the hold capacitor – is greater or less than the D/A converter voltage.
At first, the most significant bit (MSB) is on, setting the D/A converter's output voltage to midscale. After the comparator output has settled, the SAR turns off the MSB if the D/A converter's output is larger than the analogue input, or keeps it on if it is smaller. The process repeats with the next MSB and this binary search continues until every bit in the register is tested. The resulting D/A converter input is a digital approximation of the sampled input voltage and is output by the A/D converter at the end of the conversion.
Some A/D converters that operate with multiple supplies have well defined power up sequences and AN-932 provides a good reference for designing power supplies for these converters. Special attention should be paid to the analogue and reference inputs; typically, these should not exceed the analogue supply voltage by more than 0.3V. Thus, AGND-0.3V<>
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While it is commonly believed that SAR A/D converters have no latency delay, some have such a delay for configuration updates, so the first valid conversion code may be undefined until the delay – which may be several conversion periods – has passed.
The AD7985 features two conversion modes: turbo and normal. Turbo mode, which allows conversion rates of up to 2.5Msample/s, does not power down between conversions, so the first conversion contains meaningless data and should be ignored. In normal mode, however, the first conversion is meaningful.
For the AD7682/AD7689, the first three conversion results after power up are undefined, as valid configuration does not take place until after the second EOC. Therefore, two dummy conversions are required (see fig 3).
When using the AD765x-1 in hardware mode, the logic state of the RANGE pin is sampled on the falling edge of the BUSY signal to determine the range for the next simultaneous conversion. After a valid RESET pulse, the AD765x-1 defaults to operating in the ±4×Vref range, with no latency problem. If, however, in the ±2×Vref range, one dummy conversion cycle must be used to select the range at the first falling edge of BUSY.
Some oversampled SAR A/D converters have postdigital filters that cause additional latency delay. When multiplexing analogue inputs to this type of converter, the host must wait for the full digital filter settling time before a valid conversion result can be achieved; after this, the channel can be switched.
Last, but not least, the host can access the conversion results through some common interface. To get valid conversion data, make sure the digital interfacing timing specifications in the datasheet are followed.
Steven Xie is an A/D converter applications engineer with Analog Devices' China Design Centre.
