Expert panel discusses the definition and practicalties of IP design reuse

Today, the trend is towards subsystem IP, where an increasing number of pre integrated and verified blocks perform a specific complex function. IP blocks are certainly reused in subsystem IP, as well as in SoC designs. Subsystem IP can help SoC designers save development and verification time and cost. Yet, according to many vendors, it still allows plenty of room for product differentiation. In general terms, one misperception of IP design reuse is that while an IP block maybe reused extensively, it is rarely reused in exactly the same configuration, even by the same customer, because performance targets and constraints change, standards evolve and new processes appear. Then there is configurable IP, which gives designers some room for customisation, while broadening the concept of design reuse. "IP has to appeal to a wide range of users to be truly reusable or it has to be configurable," said Joachim Kunkel, general manager of Synopsys' Systems Group. Grant Martin, chief scientist of IP specialist Tensilica, recently acquired by Cadence, concurred, adding: "Our customers have been reusing our configurable IP successfully for years." But reuse does not detract from Tensilica's IP development road map. "Customers always want to see big leaps in performance," he said. ARM is one of the most successful IP vendors. John Goodacre, director of Technology and Systems, commented: "We are not just talking about the IP itself being reusable, but also the ideas behind the physical device that are reusable. Some ARM IP is still being reused six years on." That doesn't mean all ARM cores look the same, he said. "There is nearly always some configurability in our IP, although the instruction set is stable." He added that some configurable features become stable, standard features over time. Synopsys also offers configurable IP. "Some IP even has to be customised for different metal stacks," Kunkel said, adding that such customisation is done very carefully in the factory. "Typically, with configurable IP, we ship IP to the customer according to certain prespecified parameters, which are programmed into the mask," he explained. Process and standards changes Even popular IP blocks need to be changed for every new process node or fabrication process. Kunkel said IP reuse implies that a design has been used at least once and is effectively 'on the shelf'. "But this is not always the case!" In helping customers prepare for the next design node, say 20nm, Synopsys is having to design IP early. "We can show the silicon is functional, but process rules will continue to change, so we are still tweaking the design." But he agreed the IP will be reused, eventually. Meanwhile, standards based IP has traditionally been considered to be the most likely and easily reused. Typically, these are 'must have' blocks – with functions such as USB3, 1000BaseT Ethernet or PCI Express – that are not product differentiators. Some of these standards include hundreds of requirements, all of which need to be considered when the IP is developed, and there can be dozens of additions during the evolution of each standard, which may require modifications to 'standard IP'. For this reason, vendors often create IP that is 'designed for change', to ensure it can be optimised to meet evolving standards, as well as the end application. New IP also needs to be preverified in order to be classified as 'off the shelf' and 'reusable'. Subsystem IP Other vendors have made a business out of developing more complex, high value IP – sometimes dubbed platform IP – which they sell to multiple customers. This has largely evolved to become subsystem IP. Tensilica is moving beyond configurable IP blocks to subsystems IP, particularly for audio functions. "These are still configurable and reusable," Martin confirmed. "Audio is no longer a standard function. Now, we need to support hundreds of audio codecs, where there used to be just 10 or so." He emphasised the ability to select the required codec for an application is important. On subsystem IP, Martin commented: "The processor core is the NAND gate of the 21st Century." However, he believes that not all subsystem IP need be cpu based. "Subsystem IP is a much bigger development risk. You have to work with the customers and they are taking more risks too." He added that some customers now have less skill at the rtl and back end levels than before, preferring to rely on the IP vendor for support. Kunkel agreed. "Subsystem IP needs to be developed in conjunction with the customer and the foundry. It's a three way process which is all about the risk-reward equation." He sees it as a trade off for all parties. "The risk is not always that the IP won't work, but it won't work sometimes – the corner cases are critical." From the vendor perspective, highly specialised subsystem IP may not have many takers. "And putting together a subsystem with IP from different vendors can be fraught with legal problems," he added. Conversely, Martin believes large subsystem IP has much potential for reuse. "Engineers can differentiate a design in other ways. We have certainly found application areas where large subsystem IPs have already been reused." Plug and play In the early days of IP, the idea was that all blocks, whatever their function or source, could be integrated using standard 'hooks' or interfaces. This 'plug and play' concept was the key to reuse. Martin: "ARM's AMBA bus was a great help in this respect." Kunkel agreed. "AMBA has been a major enabler." Goodacre pointed out that, as IP blocks, buses and the interconnect structures have become more complex and with many more blocks to integrate, other solutions have had to emerge. All the panellists agreed that IP-Xact has become the de facto approach, not only because it allows IP to interoperate, but also because it allows information to be shared between different design environments. IP vendors believe that time to market benefits alone will drive wholesale adoption of the IP-Xact wrapper standard. "Today, all Synopsys IP is shipped with the IP-Xact wrapper," Kunkel noted. "IP-Xact is a great help," Goodacre added. With blocks getting more complex, he explained, designers need all the help they can get to reduce verification time and effort. "And there are some very specialist parts in our Lego kit!" he added. In summary, IP design reuse is very much alive. However, IP may be designed to be configurable, thereby enabling some customisation within the definition of design reuse. Further, the trend towards subsystem IP does not detract from the concept of IP design reuse. Meanwhile, the adoption of interoperability standards, such as IP-Xact, remain a critical enabler of IP use and reuse, the panellists concluded.