FPGA industry rises to the challenge of 28Gbit/s transceivers

It was a moment eagerly awaited by telecom and datacom vendors, for whom the advent of 28Gbit/s electrical interfaces will enable compact, cheaper 100Gbit/s CFP2 optical modules for use as pluggable interfaces on forthcoming denser switching and transport platforms. The first CFP2 optical modules, expected in 2012, will use a 4 x 28Gbit/s electrical interface, instead of the 10 x 10Gbit/s lanes used in the current CFP device. The CFP2 will be half the size of the CFP module. The CFP requires a 'gearbox' ic to translate the 10 x 10Gbit/s of input data into four 28Gbit/s lanes, which are then converted to a 100Gbit/s optical signal sent over fibre. This gearbox ic will be scrapped once the CFP2's 4 x 28Gbit/s electrical interface is adopted. Both Altera and Xilinx have announced fpga families with 28Gbit/s transceivers. Altera's Stratix V GT family has 4 x 28Gbit/s and 32 x 12.5Gbit/s transceivers per device, with engineering samples available since August. Xilinx' Virtex-7 HT family, available from mid 2012, has devices with eight or 16 x 28Gbit/s transceivers and up to 72 x 13.1Gbit/s transceivers. "The real driving factor [for 28Gbit/s fpga transceivers] is people wanting to interface to the CFP2 module," said Craig Davis, product marketing manager at Altera. "We are working with several customers on next generation systems: 100G, 2x 100G and 400G systems," said Panch Chandrasekaran, senior product marketing manager for high speed serial I/O at Xilinx. Demand for the high speed fpga interfaces is also coming from medical and military applications. Xilinx says radar arrays require multiple high speed interfaces to transfer pooled data streams for processing. Developing a chip with multiple 28Gbit/s transceivers alongside digital logic presents a significant design challenge for the vendors. Operating at such a high bit rate means the transceiver designers must meet stiff signal integrity requirements. Vendors develop several generations of test chip to assess transceiver performance before moving to fpga production. A year ago, Altera showed a 28Gbit/s transceiver test chip featuring three 14.1Gbit/s transceivers that generated noise. "You learn lessons from those [tests] and they get brought into first silicon, which is what we are seeing now," said Davis. Xilinx is currently assessing the signal integrity of its 28Gbit/s transceiver test chips. "When integrating a 28Gbit/s transceiver, you have to worry about a few things, the top-most being jitter," said Chandrasekaran. "You have noise on your signal that closes the timing margin. If you have a lot of jitter, you'll have errors in your system that you can't correct." With 10Gbit/s protocols, the bit duration is 100ps, while the jitter margin is typically 35ps, said Chandrasekaran: "With 28Gbit/s, the entire bit period is 35ps, and the jitter margin is typically 10ps." Xilinx says the jitter performance of its latest test chip is 6ps. The transceiver design is being taped out and will be integrated on the fpga, for availability in the first half of 2012. Several aspects of the design must be tackled to meet the required jitter performance. One is to minimise the random jitter generated by the circuit design components. "Random jitter is just that, which means that, over time, some effects could move the clock pulse such that you miss a bit," said Davis. To reduce random jitter, the electronics that affect the transceiver signal must be designed carefully, he said. The transceiver's clock source must also be extremely clean. To achieve a clock source with low phase noise, an LC tank oscillator is used. "It has its own contribution to random jitter," says Davis. "But it is really important as it is the clock source – anything on that [clock] will go through everything else." Such noise contributes a deterministic component to the jitter. Deterministic jitter is caused by noise from power supplies or noise coupled from the clock, and that you may see on the [signal's] edge," says Davis. The quality of the clock design and the noise it picks up also impacts the overall transceiver count on the fpga. "When you build high quality clocks with inductors (the L in LC tank), you can only put in so many of them and you can only put them so close to each other, as they have a tendency to 'chat' and you want to avoid that," said Chandrasekaran. Another design issue for the 28Gbit/s transceiver is the need for pre emphasis and equalisation to boost the signal's high frequency components. "That is what allows us to compensate for the losses that occur on the link," said Davis. Altera and Xilinx use different approaches to minimise the noise picked up by the 28Gbit/s transceivers. Xilinx uses its stacked silicon interconnect technology such that the 28Gbit/s transceivers are on a separate die to the digital logic and lower speed 13.1Gbit/s transceivers. "With 28Gbit/s and fpga logic on the same die, noise coupling is going to kill you, especially when the fpga is full up," said Chandrasekaran. Davis says Altera uses proprietary solutions to minimise noise from a fpga's circuitry to the transceiver, but it hasn't disclosed details. "We believe we have a very good solution that has the benefit of being proven by interoperability beyond the specification," said Davis. He also argues that a monolithic die design benefits overall power consumption, while signal integrity and crosstalk between the parallel bus to the transceivers are better. Altera says it is tracking standard developments to determine how it will expand the line rate and number of transceivers on future fpgas. One emerging need that may push up the line rate is the need for a stronger forward error correction (FEC) code for Optical Transport Network optical transmission. This may require the transceiver to go beyond 28Gbit/s in order to accommodate the extra FEC overhead, said Davis. Altera has already detailed plans to add optical interfaces to its fpgas (NE, 24 May 2011) and will be showing customers the fpga optical demonstrator from October. Xilinx stresses that fpga transceiver speeds can be increased. "Electrical interfaces are not the bottleneck," said Chandrasekaran. "You can design chips that run at 50Gbit/s; you can do that with great difficulty, but we can do it with technology that exists today." The limitation is distance. "Transporting 25Gbit/s over a few inches is hard enough, that is why you go to optics for longer distances," said Chandrasekaran. But Xilinx says the use of optics for high speed fpga interfaces raises other challenges, such as issues of cost, form factor and reliability. "There is a lot of interest in optics and how it is going to get integrated into silicon," said Chandrasekaran. "That will be the next challenge."