FPGAs back design call

Even with such assurances, challenges remain. The chip must be flexible enough to meet the requirements of more than one system vendor and the device must, ideally, work first time to avoid costly redesigns. Such considerations help explain Galazar Networks' decision to launch a reference design for its MXP2 multiplexing and mapping chip, even before the chip is taped out. With its MXP2-F reference board, Galazer has implemented a subset of the functions of the MXP2 design using three large fpgas. So, while the reference design supports mapping Sonet/SDH clients to OTN, it doesn't support mapping other clients, such as Ethernet, storage or video, to Sonet/SDH first and then into OTN. Using fpgas allows functions such as clock recovery and forward error correction (fec) to be verified prior to tape out. "Certain functions in this design, like fec, are difficult to verify using simulation [tools] alone," said David Kirk, Galazar's vice president of marketing. "We are striving to avoid respinning the design." Using the reference platform allows Galazar to deliver the design to its customers earlier, enabling system vendors to demonstrate working hardware to their customers. System vendors provide further verification of the MXP2 design and may decide to go to market sooner using the fpga based design on a line card. Nortel says there are advantages in using an fpga based reference platform for specific designs. "It allows software work to be started and removes risk from the silicon – and the project – early in the design cycle," said Hugues Tournier, a hardware design architect at Nortel. "We like the step Galazar has taken," said Mohamad Ferej, vp of R&D at Transmode, "and would like Galazar to use this IP strategy for more devices." Transmode's appetite for IP stems from its preference for using fpgas in its line card designs. The firm buys IP blocks from third parties while developing its own IP for functions it considers 'strategic'. Transmode favours fpgas because chip companies can be reluctant to respin an assp, even after a bug is found; especially if a major customer is satisfied with the chip. In contrast, fpgas allow platform features to be added and bugs to be fixed using software upgrades. "An fpga based strategy is powerful," said Ferej. "It's a huge advantage to be able to send a software patch and upgrade remotely." Galazar's MXP2-F reference platform combines hardware with real time operating system support. The hardware comprises Freescale's PowerQuicc II MPC8270, three Xilinx Virtex-5 LX330T fpgas, two Broadcom BCM8152 10Gbit/s multi rate transceivers for the line side, and 10 Silicon Labs Si5326 jitter attenuator and clock multiplier ics for client side signals. The board comes with Galazar's device manager and service manager software executed on the PowerQuicc. The device manager oversees the board's functionality, downloading code to the fpgas, monitoring services and collecting data statistics. "If the board is carrying an SDI video signal, it checks that the client signal is valid and reports any errors in the frame," said Kirk. Service manager software, which views the board as a network element, delivers such features as remote card management and protection switching. "Larger [system vendors] tend to have their own [node management] software, but we developed it to test the device and board as a full node, and for those smaller [system] customers that don't have their own [node management] software," said Kirk. The MXP2's main function is to multiplex various client side signals – from 125Mbit/s to 4.125Gbit/s – into one or two 10Gbit/s line side interfaces and to demultiplex the various client signals received from a remote node. A key feature is restoration of the timing information in each transmitted client signal. There are three signal timing options. The simplest is to use a local reference clock with no relation to the transmitted clock. Alternatively, the clocking data of the transmitted 10Gbit/s Sonet/SDH signal is restored but, in the process of multiplexing the client signals into the higher speed frame, individual timings are lost. The third, most complex, case is transmitting clocking information of each signal with its data. "This [multirate clock recovery] is not difficult to do, but you need to meet tough jitter requirements – especially for Sonet/SDH and SDI signals," said Kirk. With developments like synchronous Ethernet planned for use in backhauling cellular basestation traffic, transferring accurate timing data is a must if handset calls are not to be dropped. Ferej points out that chip companies have now mastered multirate clock recovery, but says fpga vendors are always one step behind. "There are no fpgas with good quality integrated 10Gbit/ clock data recovery," he said. That is why fpga designs use external clocking ics for the high speed signals. But Nortel's Tournier warns there is a difference between the clocking performance of an fpga design and the final assp. "Even I would not suggest using measurement results from the fpga to leapfrog to final silicon," he said. "Especially when results from the datapath, jitter performance from the serdes and the 'clock tree' architecture will all differ between the fpga and final silicon." Galazar's reference design is aligned with Xilinx' targeted design platform programme, which according to Kirk, engages IP suppliers to develop whole systems that include software as well as integrated IP blocks to simplify system development for customers. Xilinx points out that fpga designs include common building blocks, such as I/O interfaces and processor peripherals, that can account for up to 80% of a design. Its targeted design platform strategy combines and validates common IP and the reference design such that a customer can quickly develop the bulk of a design and focus on differentiation. So will Galazar come out with fpga based reference platforms for all its future assps? "No," said Kirk, "it all depends on the complexity and newness of a design. If the device is not complex or is based on an old block, detailed simulation is enough," he concluded. Galazar's MXP2 The 20Gbit/s MXP2 multiplexes and maps between up to 11 client facing interfaces and two network facing SFI-4.1 ports: either as an OC-192 Sonet (10Gbit/s) signal or an OTN OTU-2 format. OTU-2 wraps data into a framing format that includes fec to boost the signal's optical transmission reach. Client side interfaces include an SFI-4.1 port supporting 10Gbit Ethernet/ Fibre Channel or a Sonet OC-192 signal. The remaining ports support combinations of Sonet/SDH, Ethernet, storage protocols and various video formats. The MXP2 is targeted at multiservice provision platforms, which multiplex traffic parcelled into OTN frames for optical transmission, and at reconfigurable optical add/drop multiplexers that pick up or deliver optical lightpaths at metropolitan network nodes (see NE, 23 September, 2008).