So it's no surprise to find EDA companies addressing the problem via FPGA based prototyping systems. Synopsys says it has been delivering them for more than 10 years, during which time it has evolved the product through six generations.
Its offering is the HAPS – short for high performance ASIC prototyping systems – family, designed to help teams get their products to market more quickly and, importantly, to avoid costly respins.
But Synopsys is not alone in the field. Rival EDA vendor Cadence Design Systems has just launched its Protium system and believes this represents the 'state of the art'.
Protium forms part of Cadence's System Development Suite (SDS), a set of four platforms intended to accelerate the integration, validation and bring up of designs (see fig 2). According to Cadence, design teams can speed system integration time by a factor of two using the Suite.
Frank Schirrmeister, director of product management and marketing for Cadence's system and verification group, said: "Protium is another step in the development of the System Development Suite, which features a set of engines addressing simulation, emulation and FPGA prototyping. We announced SDS in 2011 and have updated it each year since. Now, we're adding an FPGA based rapid prototyping platform."
But it's not Cadence's first offering in this field. "We had a previous system called RPP," Schirrmeister noted. "That was based on Altera FPGAs."
In fact, Schirrmeister points to a portfolio of products that address the general verification challenge. "We have Palladium and Protium," he noted. "Both share the same software front end, but the difference lies in their respective capacities, hardware debug and speed." Palladium is the larger offering, capable of handling designs with up to 2billion ASIC gates, but is more akin to a simulation engine. Protium, the speedier of the two, supports performance optimisation.
Juergen Jaeger, senior product marketing manager, explained Protium's benefits. "It offers the ability to deal automatically with even the most complex clocking schemes and unlimited numbers of design clocks. Typically, rapid prototyping systems have had severe limitations in this respect. Protium also handles memory upload and download more efficiently; something which is useful for software development purposes. Finally, it supports 'by construction' elimination of FPGA hold time violations."
Yet Protium has a 100m gate design limit, whereas HAPS, for example, can deal with designs with up to 144m gates. Why this discrepancy?
Schirrmeister explained: "The average design sizes of processor subsystems is around 75m ASIC gates, so 100m gates is the right place to stop. Larger designs need to be handled on an emulator."
Jaeger pointed to a system related reason. "The 144m gates on a HAPS system is achieved by the user having to connect three HAPS boards together and then having to partition the design manually between those boards. With Protium, this is done automatically. Protium users can connect multiple systems together to generate a system with more capacity if they want to."
Protium and HAPS do have a common element: the use of Xilinx FPGAs. Both systems use the V7-2000T, each of which can handle around 12.5m gates.
The entry level Protium configuration has two FPGAs, allowing designs of up to 25m gates to be processed. However, Protium can accommodate up to eight FPGAs, providing the 100m gate capacity.
There are two baseboard options, with two and four FPGAs, and Protium can accommodate two boards per chassis. Using Protium is said to allow design bring up to be four times faster. It also has four times the capacity of the RPP system and three times as much memory. In all, Cadence says there is a fivefold improvement in compile time when the Palladium design flow is applied.
"The key difference between Protium and other systems in the market," said Schirrmeister, "lies in the fact that we provide a hardware and a software platform. We have taken the front end from the Palladium system and ported parts of it to the FPGA system. This means Protium has an automated flow that helps to get the design up and running significantly faster; we say weeks, rather than months.
"But if the user wants to optimise the design manually for speed and capacity, Protium allows this."
There are three steps in the Protium flow. The first is to import, compile and synthesise the design. Then, the design has to be partitioned across however many FPGAs there are. At this point, Protium converts gate clocks and latches into FPGA friendly structures, amongst other things. This generates one individual netlist per FPGA for subsequent place and route, as well as a verification model for validating design functionality. Finally, FPGA place and route generates individual bit files for the FPGAs.
Protium's performance is also adjustable. In its fully automatic configuration, Protium operates in the range from 3 to 10MHz. However, when manual guidance is selected, the system can run at speeds of up to 30MHz. A further option is what Schirrmeister called 'black boxing'. In this configuration, there is direct clock mapping and directly connected bulk memories, that speed system performance towards 100MHz.
Protium is cycle based, updating each net in the design once per cycle of a conceptual clock called FCLK. This is generated automatically by the compiler, which also determines the frequency. Cadence also claims compete clock tree transformation and says this eliminates FPGA and board clocking restrictions. By removing these restrictions, it adds, FPGA place and route is speeded and better quality results are obtained.
According to Cadence, FPGA based prototyping continues to attract more users. Most of those using emulation are also taking advantage of FPGA based prototyping, whilst 80% of digital ASICs are prototyped using FPGA based systems. "More than half of prototyping users see bring up time as their main challenge," Schirrmeister asserted.
And this is one of the highlights for Protium, in Schirrmeister's view. "This area is challenging," he admitted, "with issues including memory modelling and partitioning. Teams can spend a couple of weeks taking the RTL and putting that into an FPGA system; they need to change the RTL model and the memories. Once they've done that, the team needs to validate that the result is what was expected.
"With the flow from the Palladium front end, memory creation, clock handling and partitioning are all handled automatically."
There is also the option to use Palladium at some point in the process. "If you find a bug because you have changed the RTL," he continued, "you might find the FPGA based approach has limited capabilities; it's not as good as simulation or emulation. So users can take the netlist and bring it up in Palladium more quickly."
Will Protium get more capacity? "The sweet spots for capacity between FPGA based prototyping and emulation will likely change in the future," Schirrmeister concluded.
