These include the Palladium Z3 Emulation and Protium X3 FPGA Prototyping systems, a revolutionary digital twin platform that builds on the Palladium Z2 and Protium X2 systems to tackle escalating system and semiconductor design complexity, and to accelerate the development timeline for the most advanced SoCs.
The Palladium and Protium systems have been long used by AI, automotive, hyperscale, networking and mobile chip companies and, targeted at the industry’s largest multi-billion-gate designs, the latest Palladium Z3 and Protium X3 systems will provide customers with more than a 2X increase in capacity and a 1.5X performance increase compared to previous-generation systems, enabling faster design bring-up and shortening overall time to market.
“As generational drivers accelerate the need for system and semiconductor innovation, our customers are facing increasing challenges to power the most advanced applications,” said Paul Cunningham, senior vice president and general manager of the System Verification Group at Cadence. “The third generation Palladium and Protium dynamic duo systems are core components of the Cadence Verification Suite and interface with the Verisium AI-driven Verification Platform. The Cadence verification full flow offers our customers the highest verification throughput needed to deliver their hardware innovations to market faster and to support the rapid development of new technologies, such as generative AI.”
The Palladium Z3 and Protium X3 systems offer increased capacity, and scale from job sizes of 16 million gates up to 48 billion gates, so the largest SoCs can be tested as a whole rather than just partial models, ensuring proper functionality and performance.
These systems are powered by the NVIDIA BlueField DPU and NVIDIA Quantum InfiniBand networking platforms and maintain congruency when transitioning between the two systems and transitioning from virtual to physical interfaces and vice versa.
The Palladium Z3 system accelerates hardware verification, and through functional and interface congruency, models can be quickly brought up onto the Protium X3 system for accelerated software validation.
“The supercharged Palladium Z3 and Protium X3 are built to deliver fast pre-silicon verification and validation of the largest and most complex devices,” explained Dhiraj Goswami, corporate vice president, Hardware System Verification R&D at Cadence. “Our innovative custom silicon and system architecture, combined with revolutionary modular compile and debug capabilities enabling multiple turns per day, continues to push the envelope to meet our customers’ needs, allowing them to solve the world’s toughest challenges and enable their next generation of innovations to become a reality.”
With the Palladium Z3 system’s new domain-specific apps, users have access to one of the most complete offerings for managing increasing system and semiconductor design complexity, improving system-level accuracy, and accelerating low-power verification. The domain-specific apps include the industry’s first 4-State Emulation App, the Real Number Modeling App, and the Dynamic Power Analysis App.
"As SoCs become more complex, scalable validation and verification tools that enable massive software testing before tapeout are more critical than ever," said Tran Nguyen, senior director of design services, Arm.
