Framer-Mapper looks to serve future comms needs

On receiving first samples of a framer-mapper design, AppliedMicro typically sends several to each of its telecom equipment customers. But it has received requests in the thousands for its latest Yahara chip family, according to cto of transport Subhash Roy. While Roy admitted the company is working with all the leading telecom optical transport equipment makers, that would account for hundreds of samples at most. What may explain the extra demand is that the 10Gbit/s bidirectional Yahara can also address 40Gbit/s and emerging 100Gbit/s optical transport designs, requiring four and ten Yahara chips per line card respectively. The design goal for Yahara – AppliedMicro's fifth generation 10Gbit/s OTN framer-mapper – is to extend Ethernet, traditionally a local area networking technology, to span metropolitan (up to 800km) and long haul (up to 2000km) optical networks. Although targeted at telecom operators, the part also addresses the needs of multinationals with private networks in the form of unlit – 'dark' – fibre. Indeed, Yahara's origins stem from such end users. "We talked to non traditional end customers that wanted to transport Ethernet point to point, mapping Ethernet into OTU-2 [frames] not SONET/SDH [transport]," said Roy. OTU-2 is a 10Gbit/s framing format, part of the Optical Transport Network (OTN) standard that frames various data and adds forward error correction (fec) to boost transmission distances. Such discussions led to what AppliedMicro calls a 'packet over glass' design, demonstrated in 2006 and since refined. "We kept asking what should be added to make it succeed and drive down costs," said Roy. The result is the Yahara family, comprising three devices. Market research firm LightCounting views Yahara as an 'encouraging sign' for the telecom transport industry, pointing out that it is one of only a few major framer and fec developments since the end of the telecom downturn in 2003. But it is not the only framer-mapper being developed; others in the market include Cortina Systems, PMC-Sierra and Galazar. According to Michael Zapke, chief architect of transport platforms at Nokia Siemens Networks, assp companies are thinking twice before creating new chip families, given the evolution of fpga technologies. "The number of conventional assp projects is decreasing, while more virtual components – IP cores – are becoming available," he said. Yahara maps 10Gbit/s protocols, such as carrier Ethernet, SONET/SDH (OC-192 and STM-64) and 8G and 10Gbit/s Fibre Channel, into OTU-2 frames. While the different protocols may be rated at 10Gbit/s, each has its own rate and AppliedMicro uses the ITU's generic mapping protocol (GMP) to map the protocols to OTU-2 frames. Yahara also supports two fec schemes: the G.709 fec, part of the ITU OTN standard, and AppliedMicro's enhanced fec, the ITU G.975.1.I4. There is a rumour that Yahara also includes a proprietary fec, enabled for one system vendor customer. Several features and on chip integration have been employed in the Yahara design to reduce system costs. AppliedMicro has integrated a PHY and clock synthesising circuitry so only one external clock is needed. Such techniques, claims AppliedMicro, halve board space and cost while reducing the board's power consumption by more than 40%. These savings are based on a comparison between a traditional line card – featuring a separate framer-mapper and PHYs and a 300pin line side transponder – with a Yahara S10126 based line card (see box) employing a smaller, XFP pluggable transceiver for line side transmission. Other system cost reduction techniques include the use of an fpga interfaced to a Yahara S10124 to add protocol specific functions. "You get huge amounts of flexibility [interfacing the fpga] without needing specialised cards," said Roy. An fpga is interfaced via the S10124's 4bit system interface and SFI-4.1 interfaces, while the two XFI interfaces support the line side and client side pluggable optics. The Yahara features an internal input-output cross-connect to link the device's four interfaces. One use for the fpga is to send spoof Fibre Channel acknowledgement signals to avoid continual data retransmissions: the storage protocol waits for an acknowledgement signal before sending the next block and the latency across long haul links is lengthy. Another task the same fpga can undertake, by loading a new profile, is AES data encryption. Yahara can also tackle emerging 100Gbit/s transmission requirements. "We believe the market from 100Gbit/s will be driven by aggregating 10Gbit/s, not with a 100Gbit/s interface on a router blade [as drove the 40Gbit/s market]," said Roy. One clock, rather than 10, is used and the need for costly on chip buffering to accommodate asynchronous 10Gbit/s streams is avoided. The downside is that all 10 streams must be dropped to recover a data stream; individual 10Gbit/s streams can't be broken out. Yahara's use of an fpga and its ability to address higher speed transmission rates is applauded by Zapke. "Both ideas make a design more robust against changes in the standards and allow a catching up with future features and bandwidth enhancements," he said. Pre-emphasis – the distortion of signals prior to ensure better transmission characteristics – and electronic distortion compensation for received signals have also been added. Used together, they extend the distances before signal regeneration is needed. "Generally, a laser with a 120km reach can now go 160km," says Roy. Engineering samples for all three Yahara devices are available and AppliedMicro is on target for volume production by year end. Yahara is being designed into new line cards for existing deployed platforms, as well as for next generation systems. As for the roadmap, AppliedMicro says it is developing a higher density framer-mapper for long haul packet optical transport platforms. Verizon has issued a specification for such a platform that supports carrier Ethernet and SONET/SDH. The US operator wants to consolidate its network using two main classes of packet optical transport platforms, for metro which it is already deploying and a newer long-haul version it first detailed this year. The Yahara family Three devices make up the Yahara family. The S10124 is the most complex, targeted at multiservice transport platforms that map various client side signals for transmission over metro and long haul networks. The device features two XFI electrical interfaces and one SFI-4.1. XFI supports XFP and SFP+ pluggable optical transceivers, while the SFI-4.1 is used to interface a 300pin optical transponder. The S10124 also has a four channel wide system interface supporting the XAUI, SFI-4.2 and SFI-5 interfaces; the interface used to link an fpga. The S10124 comes in a 25 x 25mm plastic ball grid array. The S10123, supplied in a 19 x 19mm package, is aimed at metro Ethernet and switch router platforms and differs from the S10124 in having one XFI and one system interface only. Lastly, in the S10126, the system interface is stripped off, but it includes two XFI interfaces. The device, also 19 x 19mm, is small enough to fit behind an XFP. According to Roy, several service providers have even enquired about integrating the Yahara chip within an XFP module.