Power verification is just as important as functional verification for complex SoCs

Analysis of power characteristics and verification of power management functionality have been employed to reconcile these opposing vectors –first at the gate level and then at the RTL. But these approaches fall short for both system level verification and applications that require real world stimulus. With gate level verification, simulations are slow, while debugging is difficult, takes longer and requires more resources. Meanwhile, RTL simulation using directed unit level tests on individual blocks provides neither the completeness nor accuracy required for full chip power verification and analysis. Because power is impacted by software and hardware, low power verification and power analysis must be done at the system level on the full chip, applying real world applications and long test sequences. Emulators have the speed and capacity to pull in the full design environment, even for 1billion gate designs, apply real world stimuli – including application and embedded software – and run many sequences. Mentor Graphics' Veloce system has two primary aspects, which can be used together or separately. Low power verification ensures that power management techniques were implemented correctly and that the power functionality of the design is correct. Power analysis calculates average and peak power to help design efficient batteries and to avoid such things as over or under specifying SoC power requirements. Low power verification Emulation enables designers to conduct power related verification at the system level with software and hardware running simultaneously. Test sequences can be sent from software and executed by the hardware. Designers can also boot an operating system and stress test the design quickly through a large number of power sequences. The growing number of SoC power domains is one reason why emulation is essential for complete and accurate low power verification. Only emulation has the speed and capacity to repeatedly exercise a large number of power domains and, because the whole SoC is mapped into the emulator, it can mimic low power functionality using real stimuli, providing a higher confidence in the completeness of verification than is possible with simulation. Various power management design techniques can minimise power consumption. At a conceptual level, these involve: • switching off power domains that are not needed for specific SoC functionality to reduce leakage current, and • creating multiple voltage domains to trade off power requirement and performance Verifying these low power management techniques have not impacted the design functionality requires modelling and thorough verification of: retention; corruption; isolation; and level shifters. Veloce provides support for all of these verification and modelling tasks (see fig 1). Retention flops and latches ensure that power domains return to a known good state when powered up, but retention cells are expensive so designers seek to insert the minimum number of cells necessary to retain critical states in the design. Because emulation runs long tests using actual application stimuli in the full design environment, it can verify that a design behaves correctly after insertion of the retention states. A power domain in sleep mode is verified by corrupting all the states in that domain when it is switched off. To improve corruption coverage, emulators like Veloce provide four kinds of corruption models: All 1; 0; Invert; and Random. With run time control, designers can choose between the four models, further increasing corruption coverage, with dynamic assertions inserted automatically to check for specific cases. The use of corruption models and assertions creates confidence that, when the chip is fabricated, things will work correctly. Isolation cells determine the values of a power domain's input or output port when the domain is powered down. Even though they may represent different power domains, when one domain is turned off, it is still connected electrically to other domains. Emulation enables SoC designers to verify that isolation cells are inserted at all the required locations and that they drive correct values during a domain's power off state to prevent corruption of downstream active logic. Multiple voltage domains allow designers to use lower voltages whenever possible while using higher clock speeds only when necessary. Designers insert level shifters to swing a logic value in one voltage to the same logic value in a different voltage. Level shifters must exist in all the required locations, have the right polarity and be within the correct voltage up and down range. Automatically inferred assertions, compiled in the emulator along with the design RTL, ensure each level shifter is correct in all of these aspects. Average and peak power analysis Realistic average and peak power consumption can only be determined by applying application specific stimuli. This also requires running long tests to ensure that actual power peaks are captured – neither of these can be done at the block level. Simulation can run for a few tens or hundreds of thousands of cycles and calculate average power, but such a small sample cannot produce an accurate result. Emulation ensures the accuracy of average power calculations by running real world stimuli over hundreds of million cycles. Emulation systems then produce a Switching Activity Interchange Format (SAIF) file, based on the IEEE P1801 Unified Power Format (UPF) standard, for the average power computation. The SAIF file can be supplied to any standard power analysis tool for the average power computation. Because the information in that SAIF file is reflective of the actual stimulus used in the final design, the average power consumption figure is much closer to the actual power consumption of the fabricated SoC than one produced using simulation. The first challenge in peak power analysis is to locate hot spots in a design that runs for billions of cycles. Emulation solutions, such as Veloce, address this using a sub sampling approach to narrow the peak areas of interest to a few hundred thousand cycles. Designers can then perform more accurate power analyses by sampling each clock edge within just that area of interest, creating a file system database (FSDB) or SAIF file that can be fed to a standard power analysis tool for accurate and detailed peak power analysis (see fig 2). Power analysis using emulators provides a platform where engineers can accurately calculate average and peak power. Emulation can run application specific traffic for many million, even billions of cycles, collect the data, and compute the average and peak power. The resultant power computations will be much closer to actual power consumption than is possible with simulation or manual calculations. Power verification is just as important as functional verification for today's complex, high performance SoCs. Veloce delivers a solution covering both power management and power analysis capabilities, using a single engine at the system level with flexible options for applying stimuli. It provides interfaces to standard power analysis tools and adheres to UPF standards, cutting the learning curve for new users and preserving a company's investments. Vijay Chobisa, product marketing manager, and Sanjay Gupta, group engineering director, are with Mentor Graphics' Emulation Division.