A huge shift in the capabilities of mobile computing devices requires a new power analysis flow methodology and Veloce Power Application software lets chip designers identify power concerns while running system level-tests, and then capture detailed information for focused power analysis.
The Veloce Activity Plot allows a power analysis team to run long test sequences and quickly isolate high switching regions over long emulation runs, representing actual power concerns. This enables users to run real software applications, identify areas of interest when it comes to power and then narrow down those application/logic blocks causing peak switching. An Activity Plot can be created in minutes compared to the days it previously took to create a file-based power chart.
Once high switching activity regions are identified, various sub-blocks or applications can be analyzed to determine the main source of high switching. This time zone information can be captured in a tzf (Time Zone File) file and inputted into Veloce for detailed analysis.
Dynamic read Waveform API flow
The Dynamic Read Waveform API enables accurate power calculation at the system level, where booting an OS and running software applications is required making it practical to explore power exploration at RTL for power budgeting and tradeoffs, as well as more accurate power analysis and signoff at the gate level in a targeted application environment. The dynamic API-based live streaming exchange of switching data between emulation and power analysis tools allows for all the operations to be run in parallel. Not only is it faster but it also delivers improved accuracy compared to SAIF based average flows as conditional controls are incorporated automatically for switching. The Dynamic Read Waveform API enables the power analysis and exploration possible at SoC level with long tests and scenarios that are not possible with a file-based flow
A methodology shift
By eliminating a file-based flow and providing the unique Dynamic Read Waveform API integration with power analysis tools, Veloce offers a complete RTL power exploration and accurate gate level power analysis flow. Design and verification teams can start work earlier, allowing them to do power tradeoffs and make architectural adjustments far upstream in the design cycle. Then they can continue to use the flow as the design gets frozen and gate-level representations are prepared. At that point, users can focus on more accurate power measurements and do additional fine tuning before tapeout and power signoff.
