New processor instruction set architectures (ISAs) really don’t come along very often, so open-source RISC-V ISA developed within the University of California at Berkeley has created a real buzz in the embedded industry.
The RISC-V ISA was developed on the premise that any designer could use it to create processor cores and software compilers, and the project is now run by the RISC-V Foundation, with members that include a wide range of universities and multinational technology companies (Google, IBM, Microsoft, NVIDIA and Oracle, most notably), as well as chip makers and start-ups.
The aim of RISC-V was to learn from the mistakes of other processor ISAs. The key is stability – for the instruction set and the core – which is essential for encouraging as many engineers as possible to use such open-source technology across the ecosystem, making powerful processor cores much more accessible and usable.
Application developers can optimise their code for a frozen ISA with minimal memory footprint and power consumption, but still be scalable and compatible with future devices, allowing processor core developers to work on all kinds of different implementations of the instruction set.
These will have different latencies, sizes and power consumption, but will all have an underlying compatibility with each other, and with the tools encompassed within the ecosystem.
Providing this stability across the ecosystem was a critical part of the new instruction set. This was designed with 32-bit, 64-bit and 128-bit address spaces in mind, so compatibility across them can be maintained. The architecture is also designed with extensions, to provide the customisation that chip makers need for differentiation and for future application scenarios, but the ISA’s foundations remain deliberately untouched.
Above: The U500 64-bit multicore open-source processor from SiFive
The 128-bit ISA is still intentionally undefined, because as yet there is little practical experience with such large memory capacities in embedded systems. However, the fact that the architecture will support this larger address space highlights the forward-thinking approach taken. All of this means software written for, or ported to, RISC-V will run on all similar RISC-V cores forever, giving software managers a solid foundation that preserves their software investments.
Processor cores
A wide range of processor cores are implementing the ISA, and a number of system-on-chip (SoC) devices are based around those cores.
Cores have been developed by Codasip, Syntacore, Hex Five and T-Head, while SiFive has pushed forward with a range of 32-bit and 64-bit SoCs.
SiFive launched its first RISC-V core in 2017 as a family of SoC platforms, adding support around the cores and chips. The devices are being built on a 28nm process for a 64-bit multicore Linux implementation, or on 180nm for the 32-bit low-cost IoT market with various peripherals.
The company’s Freedom platforms comprise of a complete software specification, board support packages (BSPs) to bring up an operating system, development boards and base silicon, allowing customers to create their own silicon enhancements and customisations.
The Freedom U500 series is a fully Linux-capable embedded application processor with multicore RISC-V CPUs, running at a speed of 1.6GHz or higher with support for accelerators and cache coherency for machine learning, storage and networking. This supports standard high-speed peripherals including PCIe 3.0, USB 3.0, Gigabit Ethernet, and DDR3/DDR4.
The Freedom E300 series is designed as an embedded microcontroller for the IoT and wearables markets. Based on the Freedom E310, the HiFive1 Arduino-compatible RISC-V development kit incorporates SiFive’s E31 CPU Coreplex – a high-performance, 32-bit RV32IMAC core that is capable of running at over 320MHz.
SiFive has also used the RISC-V instruction set for the S2 core IP series, with a configurable core that can be as small as 13,500 gates (in the case of the RV32E 32-bit version). The S21 64-bit embedded core has separate instruction and data buses, along with two banks of tightly integrated memory (TIM). This enables SoCs to have an always-on low-power 32-bit CPU that can be combined with a high-end 64-bit CPU that switches on when applications demand elevated performance (such as in voice-activated smart devices).
Developments of this kind help address the growing need for connected devices with machine learning and IoT, where real-time workloads have generated a massive demand for greatly enhanced embedded intelligence at the edge.
The open-source nature of RISC-V has opened up SoC design to start-ups such as Kendryte, e-fabless and low RISC, but more mainstream chip vendors are also using the technology.
Microsemi has produced some development boards for SiFive, while NXP has its own RISC-V chip. Andes Technology and Greenwave have also developed ICs around the ISA. Faraday Technology has used the ISA for an ASIC platform for the design and mass production of next-generation edge AI and IoT SoCs. It brings together the RISC-V core IP integration and SoC design verification, as well as a full-featured reference design kit consisting of real-time operating system (RTOS) and peripherals drivers, all on a 55nm process for battery-powered edge devices. This highlights how the hardware manufacturers can differentiate around a standard ISA.
Faraday has included dynamic voltage and frequency scaling (DVFS), power mode switching and fast system wake-up in the platform, but can safely include the software libraries and drivers to ensure the chips work seamlessly for specific interfacing, sensing and power-management functions.
RISC-V ISA can also be used with a wide range of tools. Microsemi has used the ISA across its FPGAs with a range of embedded operating systems such as Express Logic’s ThreadX, Huawei LiteOS and Micrium µC/OS-II. Boards include the RTG4 development kit, the PolarFire evaluation kit, etc. Debug dongles from Microsemi and Olimex, first-stage bootloaders and multiple soft peripherals are also included. Examples of drivers, firmware and projects are available on GitHub.
Another tool company benefiting from its stability is UltraSoC, which develops hardware that can be embedded in a SoC to monitor activity. This can be used for debugging the chip more effectively and even used in the field for monitoring. It has been working with Andes on integrating the monitoring hardware into the high-end AndesCore processor IP, and into an AI “supercomputer-on-a-chip” from Esperanto Technologies that uses thousands of RISC-V cores.
RISC-V challenges
Though considerable headway has already been made in relation to RISC-V’s development and proliferation, there are obstacles ahead. Researchers at Princeton University have uncovered a number of flaws in the RISC-V open-source processor core that they believe to be significant. They found more than 100 errors involving incorrect ordering of the storage and retrieval of information from memory in variations of the RISC-V processor architecture that, if uncorrected, could cause issues in software running on RISC-V chips.
The RISC-V Foundation said the errors would not affect most versions of RISC-V, but might have been more problematic for higher-performance systems.
With a common, frozen ISA across 32-bit, 64-bit and even 128-bit (when they emerge) address spaces, core developers can focus on the particular processor implementations, whether for research projects, IoT nodes or a supercomputer-on-a-chip. All these use the same compilers, the same development tools and the same debug tools, minimising fragmentation and allowing companies to keep pushing performance benchmarks rather than worrying about maintenance of multiple software products for multiple cores – and all, of course, with an open-source ethos that allows improvements to be fed back into the industry.
Extensions allow for differentiation and optimisation, particularly with regard to security, without compromising the stability of the tool ecosystem.
In this way, RISC-V allows hardware developers to focus on innovation, driven by the software needs to meet the cost, power, security and performance requirements of end users.
Author details: Mark Patrick, Mouser Electronics
