Renesas selected the AndesCore IP 32-bit RISC-V CPU cores to embed into its new application-specific standard products that will begin customer sampling in the second half of 2021.
"Renesas and Andes share the same vision to welcome the era of RISC-V being the mainstream CPU instruction set architecture (ISA) for system-on-chips (SoC),”said Frankwell Lin, President of Andes Technology. “Not only does this represent a milestone for Andes, but it marks the arrival of the open-source RISC-V ISA as a mainstream computing engine. Renesas customers will benefit from a modern ISA constructed for the needs of 21st century computing.”
“The scalable range of performance, selectable safety features, and customisation options provided by the Andes RISC-V core IP enables Renesas to provide innovative solutions for future application-specific standard products,” said Sailesh Chittipeddi, Executive Vice President, General Manager of Renesas’ IoT and Infrastructure Business Unit. “Customers looking for cost-effective alternative paths for existing or emerging applications will benefit from the reduced time to market and lower development costs.”
The delivery of Renesas’ pre-programmed ASSP devices based on the RISC-V core architecture, combined with specialised user interface tools to set the application programmable parameters, will provide customers with complete and optimised solutions.
This capability eliminates the initial RISC-V development and software investment barrier and. in addition, an extensive network of regional Renesas partners with specialised expertise will be able to provide cutting edge and sharply focused customer support.
