“It’s been the case that until now, buyers of analogue IP have had to settle for what many would describe as the least bad option from a very limited portfolio of standard IP products,” explains Chris Morrison, Agile Analog’s director of product marketing. “We’ve sought to create a new approach to analogue IP design in which we have automated parts of the design process and made the whole process of AMS design far more accessible to a broader range of engineers.”
Described as ‘revolutionary’ this automated approach to the design of analogue and mixed-signal circuits (AMS) has simplified and accelerated the design process when it comes to components like amplifiers, filters and data converters, all of which can be extremely complex and time-consuming to develop.
“Traditionally they all require manual design expertise and will involve many different iterations,” according to Morrison. “Designing for analogue is time consuming and unlike the digital domain, where it’s possible to take standard IP to deliver fixed functions, the behaviour of analogue IP can vary from one process and node to another. With digital IP it’s easy to scale from node to node.”
Using a sensor, which requires sensitivity, accuracy and stability, as an example, each design will vary from application to application while the behaviour of the analogue circuit will, in turn, vary with each process or node.
“What that means for the design engineer is that they have to, quite literally, go back to square one. There is no such thing as a standard analogue IP ‘product’,” continues Morrison. “They are in fact unique to each application, which means that they can prove costly to develop.”
Matching the digital revolution
What Agile Analog has succeeded in doing with analogue IP is to match the revolution in digital design that occurred back in the 1980s.
“Back then digital synthesis completely changed the nature of design and revolutionised the industry. Complex designs could be created quickly and then evolve along with different nodes.
“While digital design has exploded in the past thirty years, analogue design had tended to remain very much the same – little has changed, and it has essentially remained bespoke.”
That stagnation and disconnect between digital and analogue caused big problems for the industry and Agile Analog’s founder, Mike Hulse, its CTO, wanted to develop a solution that would enable faster and more reliable development of analogue ICs.
“His idea was to develop a software tool that could automatically generate an analogue IP based on a customer’s requirements and the PDK from any foundry,” says Morrison. “The software needed to be able to embrace the design tricks of engineers and be able to create accurate circuits based on whatever process the customers needed of their IP.”
To that end Agile Analog created Composa, a customisable analogue IP generator that can be used in any process to generate fully verified and accurate analogue circuits that are suitable for any process and are compliant with a customer’s exact requirements.
“There’s no need for compromise, Composa can address the power, performance and area requirements that are particular to a customer’s project,” adds Morrison.
“Composa is process-agnostic, so we can use our solution in any process to quickly generate fully verified analogue circuits.”
The tool has matured over the years and Agile Analog uses it to develop all its own in-house IP, with more functionality being added to the tool every month.
“We can also handle all the analogue-to-digital and mixed-signal boundary verification needs, which for the customer means that both the design and verification times are greatly shortened. The cost of licensing mixed-signal design tools is also made lower while integration is simpler,” explains Morrison.
He continues, “How we engage with the customer depends on them and what they are looking for. They no longer need to worry about trade-offs in their design or having to scale back requirements. With our Composa tool, we can design the exact circuit they need.
“However, communicating that to the customer can be a challenge. They’re not use to that level of flexibility, and we’re often confronted with clients who aren’t entirely sure what they want or that need to be convinced that the process actually works. I suppose we sit somewhere between being an IP company and a design services provider.”
Freeing up resources
Morrison makes the point that when a company buys Agile Analog’s IP it frees up limited design resources so they can focus on differentiating their IP from their competitors.
“The levels of innovation are currently extremely high and anything we can do to help simplify designs and speed up the design process is welcomed. You have to remember that skilled analogue designers are in short supply and that can have a massive impact on getting a product to market.”
Over the past six months the company has made some significant additions to its IP portfolio including agileADC, the company’s first customisable and process-agnostic 12-bit ADC IP as well as its first range of analogue subsystems, covering power management, PVT sensing, and sleep management which make it possible to integrate multiple analogue IPs into any ASIC by allowing the IP to be dropped straight into a digital design flow and connected via a standard peripheral bus, such as AMBA APB.
According to the company, the subsystems look just like a normal block of digital IP with the standard interfaces that engineers would expect, making them easy to understand and handle.
“Last month we unveiled our first complete analogue IP subsystem for RISC-V applications at the RISC-V Summit Europe in Barcelona,” says Morrison. “It includes all the analogue IP required for a typical battery-powered IoT system, including a power management unit (PMU), a sleep management unit (SMU), and data converters.
“As a process-agnostic, customisable and digitally wrapped analogue IP subsystem it will help solve many of the issues that System on Chip (SoC) designers currently encounter, as it pairs with a RISC-V core to form a complete solution.”
“The RISC-V architecture is enabling a surge of new SoC product developments and with our RISC-V analogue IP subsystem, it’s now possible to access the appropriate analogue IP for a specific process and foundry,” according to Morrison.
The ability to provide highly configurable analogue IP sets Agile Analog apart from most of its competitors and enables its customers to achieve their optimal design requirements.
“Our ability to re-target our IP to different process options is a major benefit for chip designers and a key differentiator for us,” says Morrison. “We take an agnostic approach which means that we are foundry- and process-independent.”
According to Morrison it’s the company’s level of customisation that sets it apart from its competitors especially in what is an extremely challenging design environment.
Agile Analog is engaged with a broad range of customers, from automotive, industrial, defence and consumer to those developing the very latest artificial intelligence enabled devices.
“AI might not seem a likely area for analogue but from an IP perspective advanced nodes need sensors across the die, they require power and routing monitoring, so analogue is required to enable these chips to perform efficiently.
“Whatever the sector, whatever the industry, we want to take the pain out of analogue design,” says Morrison. “It’s a space in which, unlike digital, the design wins can be hard to come by and are certainly hard fought.”
