The DesignWare Controller IP for PCIe 5.0 implements a 512-bit datapath width supporting x16 links to deliver the maximum bandwidth required for Achronix's FPGA. The PCIe 5.0 controller also meets Achronix's aggressive low-power and low-latency requirements.
The DesignWare DDR4 Controller and PHY IP enables high-bandwidth and low-latency memory interfaces, operating at 3200 Mb/s, a key requirement in AI systems needing high-capacity external memory. The reliability, availability and serviceability (RAS) features will allow Achronix to debug and resolve PCIe linkup issues and tailor the DDR controller to their target application.
"For our latest Speedster7t FPGAs that include a revolutionary new 2D network-on-chip, machine learning processor, 112G SerDes, and high-performance FPGA fabric, we needed to accelerate our time-to-market with best-in-class IP that offered superior features," said Manoj Roge, vice president of strategic planning and business development at Achronix Semiconductor. "The maturity of Synopsys' DesignWare IP for PCI Express 5.0 and DDR4 with advanced features that are required for high-bandwidth AI workloads, allow us to integrate the IP with confidence while focusing on our own core competencies. We are looking forward to using Synopsys' DesignWare IP including DDR5 IP in our future designs."
"As a provider of interface IP, Synopsys delivers the industry's broadest IP portfolio supporting the latest generation protocols for key applications such as AI, cloud computing and automotive," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. "Our investment in developing high-quality, silicon-proven IP solutions with differentiated features enable companies like Achronix to achieve their design requirements and build compelling products with significantly less risk."
