Socionext selected Synopsys’ HBM2E IP, operating at 3.6 Gbps, to meet the stringent capacity, power, and compute performance requirements of its innovative AI engine and accelerator system-on-chip (SoC). The Synopsys IP provides efficient heterogeneous integration with the shortest 2.5D interposer package routes.
“As a global leader in SoC solutions with differentiated functionalities, we face very tight delivery deadlines,” said Yutaka Hayashi, vice president of Automotive & Industrial Business Group at Socionext. “By leveraging Synopsys’ DesignWare HBM2E IP and integrated full-system multi-die design platform, Socionext can deliver world-class high-performance, high-capacity and power-efficient SoCs on the 5-nanometer FinFET process to the market. We are also collaborating with Synopsys on using their next-generation DesignWare IP solutions including HBM3.”
With an aggregated bandwidth of 460 gigabytes per second, the DesignWare HBM2E PHY IP delivers the required massive compute performance of SoCs in advanced FinFET processes. The HBM2E IP is part of Synopsys' comprehensive memory interface IP solution that includes DDR5/4/3/2 and LPDDR5/4/4X/3/2 IP, which have been validated in hundreds of designs and shipped in millions of SoCs.
The Synopsys DesignWare HBM2/2E IP is available in a wide range of processes from 16-nm to 5-nm.
