Adapt and tolerate

Typically, electronic devices of 2020 will have any number of unavoidable permanent defects, exhibit significant process variations and be highly susceptible to unpredictable soft errors. This was the view of a panel of electronics test experts at the recent DATE 07 conference in Nice. The discussion, chaired by Yervant Zorian, chief scientist with Virage Logic, concluded that testing such devices will be difficult, but possible. Zorian set the scene by acknowledging that many companies are already struggling to test 500million transistor SoCs. “Testing SoCs containing analogue and rf circuitry, multiple processor cores and masses of memory is a huge task.” He sees techniques such as on chip diagnostics, self test and repair through redundancy as key to mitigating the problem, not only today, but in the future. “Fault tolerance at hardware and software levels will be mandatory to provide resilience, or at least a graceful degradation, as soft errors, defects and signal integrity issues take their toll,” he said. The panel was contemplating the test challenges that ic designers might expect in 2020. Professor Antonio Rubio, from the University Polytecnica de Catalunya, painted a potentially bleak picture. “We will be close to the quantum, thermal and power dissipation limits of technology by 2020. It is going to be very difficult to test these high complexity, low power atomic level chips.”