The project will speed up the process of proving and qualifying analogue IP, and reduces the time-to-market and risk of IC development cycles through a revolutionary top-down delivery of initial IP views.
The integration of analogue IP onto a complex silicon chip is a time-consuming process and can be affected by the variable quality of currently available analogue IP products. These circuits are also very sensitive to their on-chip surroundings so issues during integration and test can lead to reliability problems. Waiting until the end of analogue IP delivery can also both slow down chip planning work, and mean that critical customer feedback is not available until it’s too late in the process.
Agile Analog has developed an in-house system to automatically generate analogue IP (including all associated IP product deliverables) to a high quality, according to customer specifications, and on any silicon process technology. This system produces a high-quality final IP delivery package (FDP), as well as an initial delivery package (IDP). The IDP is available very early and allows customers time to integrate it into their chip development process and provide feedback to be implemented in the FDP.
EnSilica’s expertise in the design of custom analogue, mixed-signal and digital chips was critical in developing a chip architecture together with a re-usable test platform that Agile Analog will now use to test and validate their latest analogue IP products.
EnSilica has integrated a number of Agile Analog’s IP products, including their latest configurable analogue-to-digital converter (ADC) IP and bandgap voltage reference IP, onto this System-on-Chip for fabrication in TSMC’s 28nm CMOS technology.
“What Agile Analog has achieved is impressive,” said Ian Lankshear, CEO at EnSilica. “The high quality of their automatically generated IP deliverables really does save integration time and effort and will benefit all their customers. Thanks to their comprehensive documentation, the integration of their analogue IP onto an SoC and the development of a test setup and procedure was effortless for our engineers, and most of our work could be done using the IDP, so we were able to get a significant amount of work done early.”
Tim Ramsdale, CEO at Agile Analog, added: “EnSilica’s extensive chip design expertise was amply demonstrated in the re-usable SoC design and test solution they created. This work will be instrumental to Agile Analog and will allow us to prove more of our analogue IP in silicon quickly and efficiently. The project also served as a pipe-cleaning exercise and EnSilica’s knowledgeable feedback and recommendations have allowed us to improve our products further.”
