The investment will allow Agile Analog to significantly expand its technology offering and sales footprint, and is being seen as an endorsement of the disruptive potential of the company’s process for generating configurable analogue IP.
Agile Analog works with ASIC or SoC manufacturers to configure analogue IP to perfectly fit their application and chosen silicon process – a marked contrast with existing offerings, which require the customer to mould their chip design to fit a limited range of one-size-fits-all, standard analogue IP products.
This financial support will provide the company with the resources to take a large share of the existing analogue IP market and to increase the availability, range and quality of analogue IP to expand the total market size to $4bn by 2025.
Agile Analog said that it will use the funding to accelerate the growth of its commercial and engineering support teams. In particular, it will immediately move to expand its team in North America, and open a Taiwan office for sales and application engineering staff serving the Asian market.
The company has also begun recruiting development engineers to be based at its Cambridge, UK headquarters and across Europe. It plans to double its headcount growing to over 100 people over the next 12 months.
Part of the funding will be used for technology development, to further enhance process support, and increase the range of analogue IP supported. Agile Analog IP is already compatible with almost all analogue CMOS processes, including advanced FINFET processes, and will expand the number of foundries supported. IP currently supported includes security, data conversion, power management, audio, signal processing and timing, and this functional coverage will be extended to satisfy increased customer demands.
Commenting Pete Hutton, executive chairman of Agile Analog, said the backing of specialist technology investors was a welcome endorsement of the company’s unique IP technology. He said: ‘The first chapter in Agile Analog’s story was about developing an automated process for generating high quality configurable analogue IP which can be verified at every stage up to right-first-time tape-out.
‘This successful funding round marks the start of the next chapter: the technology and process are proven with a range of customers from OEMs to Tier 1 semiconductor companies. So now it’s time to enable all semiconductor companies and the increasing number of OEMs who are designing their own silicon.
"Everyone is looking to shorten development cycles, increase integration, improve die area utilization and enhance system performance. By configuring analogue IP the way the customer wants it and on any process node, we can enable them to gain all these benefits. With the funding to expand our engineering and commercial teams, we can now support a greater number of customers across a wider geographical footprint.’
