This is the first in a new family of analogue IP blocks that the company is launching that are designed to simplify the integration of analogue circuits onto ASICs.
“These form part of the library of analogue IP circuits that our automatic solution generator, Composa, uses to create IP blocks that exactly match the requirements of customers,” explained Barry Paterson, Agile Analog’s CEO. “Their modular design means that they can be combined together to form sub-system solutions speeding up design times and reducing risk as they have all been thoroughly tested and verified.”
The agileOSC RC is based on a traditional architecture which allows the frequency to be trimmed to remove the effects of process variation. It can also be configured as a Free Running Clock (FRC) where a high accuracy clock is not required. With a start-up time of typically 10 us, it has a frequency range of 20 KHz to 100 MHz with an accuracy of up to +5%.
It has a low power consumption of typically 100 uA at 10 MHz which is much less than an equivalent discrete analogue component and, according to Agile, highlights the benefit of integrating analogue circuits onto the main chip.
Traditionally, analogue IP blocks have to be manually redesigned for each application and process technology but Agile Analog has developed a unique way to automatically generate analogue IP to exactly meet the customer’s specifications and process technology.
Called Composa, it uses tried and tested analogue IP circuits that are in the company’s Composa library. Effectively, the design-once-and-re-use-many-times model of digital IP now applies to analogue IP for the first time. As the analogue IP circuits in the Composa library have been extensively tested and used in previous designs, and are fully validated every time they are generated, this gives a similar level of reassurance to the digital IP world’s ‘silicon-proven’.
All the major foundries are supported including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and manufacturers.
