The company said that it had also made several enhancements to the tool’s Design Entry capabilities to boost productivity.
The new rules (62 in total) join the 97 already present in the tool’s DO-254 plug-in, and help engineers using complex hardware devices, such as FPGAs, meet specific DO-254 process objectives to receive overall system approval.
Certification authorities recommend that applicants define and follow HDL coding standards commensurate to the complexity of the FPGA design. By adhering to HDL coding standards it's easier to enforce industry best-practices and techniques to ensure high-reliability designs, prevent design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.
Commenting Janusz Kitel, DO-254 Program Manager at Aldec, said, “Unfortunately, DO-254 does not define the coding standard. This makes applicants feel uncertain in defining the proper one, especially for organisations new to DO-254. ALINT-PRO provides a comprehensive ruleset based on the best practices guidelines and experience from the industry.”
Kitel said that the expansion of ALINT-PRO’s ruleset comes at a good time for users, as a new guidance of Development Assurance for Airborne Electronic Hardware has been released. The AMC 20-152A document - already released by the EASA and harmonised with incoming FAA AC 20-152A – recommends applicants follow hardware design standards for Design Assurance Level (DAL) C projects, while previously it was required only for the most safety critical DAL A and B projects.
According to Kitel, “More designs for airborne applications will now need to define and follow an HDL coding standard, and ALINT-PRO – with its tool qualification package, used to prove the tool is capable of enforcing the coding standard automatically – can provide the necessary assurances and save engineers a great deal of time.”
The Design Entry enhancements to ALINT-PRO - enhancements that will benefit all users, whether using the DO-254 rule plug-ins or not – include:
- Optimised RAM/ROM extraction has reduced synthesis phase memory consumption
- Subprogram body checking is now supported by a number of RTL-based checkers and by an FSM extraction algorithm;
- The conversion of cores containing protected IP has been improved; and
- There is a new mechanism of CDC Assertions generation that allows users to extract the assertions through the inclusion of just one line of code (a project.generate.assertions command) in their testbench.
