Accepting a CSV file or IP-XACT register description as an input, Riviera-PRO will, working at the Register Abstraction Layer (RAL) of UVM, output files as UVM register models, RTL register models, C headers and HTML.
In addition, libraries containing pre-compiled source code compliant with the latest versions of UVM (IEEE 1800.2-2107) and UVVM (2018.12.03), plus documentation and examples, have been added to facilitate easier and better test bench creation.
“Both enhancements to Riviera-PRO are of great benefit to users,” said Sunil Sahoo, Senior Corporate Applications Engineer. “Where the automatic generation of UVM register models is concerned, it provides major time-savings – certainly when the alternative is to hand-craft hundreds or thousands of register models. As for verification methodologies, we are dedicated to the provision of the most up-to-date libraries.”
Other new features in Riviera-PRO, release version 2019.04, include:
- SystemVerilog users can create nets of integral data types (typedef);
- The SystemVerilog compiler can work with sources for which the filename (including path name) is longer than 259 characters;
- VHDL packages can be translated to SystemVerilog;
- Support for Microsoft Visual Studio 2017 has been added; and
- Debugging (Toggle Coverage analysis for VHDL) has been enhanced to include logic level transitions to and from high resistance (Z).
