This new silicon proven Universal Chiplet Interconnect Express (UCIe) subsystem expands Alphawave Semi’s connectivity portfolio and is seen as paving the way for a more robust, open chiplet ecosystem for high-performance AI systems.
Alphawave Semi’s 3nm UCIe complete PHY + Controller subsystem is capable of 24Gbps data rates, delivering high bandwidth density at extremely low power and low latency.
The solution is compliant with the latest UCIe Revision 1.1 Specification and includes a highly configurable Die-to-Die D2D controller that supports streaming, PCIe/CXLTM, AXI-4, AXI-S, CXS, and CHI protocols.
The subsystem features Bit Error Rate (BER) Health Monitoring to ensure reliable operation. The PHY can be configured to support TSMC’s advanced packaging technologies such as Chip-on-Wafer-on-Substrate (CoWoS) and Integrated Fan-Out (InFO) which maximize signal densities, as well as organic substrates for a more cost-effective solution.
“We’re pleased with the results of our latest collaboration with Alphawave Semi in the delivery of a silicon-proven chiplet-connectivity solution on TSMC’s 3nm process,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “We will continue to work with our Open Innovation Platform (OIP) partners like Alphawave Semi to help foster a robust and open chiplet ecosystem for high-performance connectivity and compute silicon solutions to enable more AI applications.”
“Achieving 3nm silicon-proven status for our 24Gbps UCIe subsystem is a key milestone for Alphawave Semi, as it is an essential piece of our chiplet connectivity platform tailored for hyperscaler and data-infrastructure applications,” explained Letizia Giuliana, VP IP Product Marketing at Alphawave Semi.
