ARM extends scalability of CoreLink SoC interconnects
ARM has extended its cache coherent network offering with the addition of the CCN-502 and 512. Both interconnects have been developed in response to increased numbers of connected devices and a consequent increase in the amount of data flowing across networks.
Ian Smythe, director of marketing for the company's CPU Group, noted: "We're seeing a lot of infrastructure changes, including content and latency. Network operators are having to answer such questions as 'how can users access content quickly?'. Different problems are being encountered at different points in the network."
The solution is said by ARM to be a single scalable architecture that ranges from high efficiency at one end of the spectrum to high performance at the other.
The CCN-502 option has been optimised for silicon area and, according to Andy Nightingale, VP of System IP marketing, has a footprint 70% smaller than the CCN-504, whilst supporting up to four CPU clusters, or 16 cores. "The CCN-512 offers maximum compute density," he added, "supporting up to 12 clusters, or 48 cores."
