‘Asic like’ architecture to underpin Xilinx’ future products
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Xilinx has launched the Ultrascale architecture, intended to take its products beyond the 20nm node. European marketing director Giles Peckham said: "Ultrascale devices, which support 20nm linear and 16nm finfet technology and beyond, will bring asic class performance to customers looking for a high level of integration and performance."
According to Peckham, each generation of programmable logic brings bottlenecks. "Routing, clocking, critical paths and power are some," he offered. "Customers want high throughput and low latency."
The Ultrascale architecture is said to deal with a number of these issues. "The number one issue is interconnect," Peckham noted. "We learned from our first generation 3d products that 10,000 interconnects are not always enough. We have extended this and made it lower latency."
However, he said the problem hadn't been solved by 'throwing metal' at it. "It's a matter of applying it intelligently," he claimed. Clock skew – another pressing issue – has been addressed using a 'more asic like' architecture with smaller clock domains. The 20nm process also consumes 30% less static power than 28nm devices.
Design closure has been improved, with the updated Vivado design software enabling utilisation rates of more than 90%.
Ultrascale also sees the end of the numerical progression of Xilinx' products. "That was synonymous with process node," said Peckham. "Ultrascale will span nodes." The Ultrascale brand will be applied to any Xilinx device made on a 20nm process and beyond.
Meanwhile, Xilinx has taped out 20nm devices and expects silicon by the end of the year. It says 16nm parts will be taped out shortly, with silicon by the end of 2014.
