electronica 2012: Xilinx looks to keep its lead at 20nm

The company's European marketing director Giles Peckham, told New Electronics: "The 20nm strategy is building on what Xilinx can offer at 28nm, where we announced a breakout strategy that moved programmable logic on towards all programmable logic, including SoCs and 3d ics." Central to Xilinx' 20nm plans is offering developers 'more bang for their buck'. In Peckham's opinion, 20nm devices will not only offer the best power/performance, they will also allow engineers to take a system level view of their designs and to get products to market more quickly. The 20nm node will see all devices made using the HPLP process developed in association with TSMC. Xilinx says it will use this process as a means of driving towards a higher level of system integration. At the 20nm node, fpgas will feature 33G transceivers and the largest device planned will have more than 100 transceivers. System level performance is said to be doubled and, by tuning the architecture, Peckham said utilisation of more than 90% would be possible without routing issues. Second generation SoCs, as the 20nm devices will be called, will move to heterogeneous multicore architectures, with optimised interfaces between the processor subsystem and the fpga fabric. Finally, 3d ics will support heterogeneous and homogeneous approaches, with wider memory interfaces and higher level transceivers; potentially 56G. Interposer technology will be critical to the 3d device and Xilinx will be offering two approaches: one supporting heterogeneous dice; the other for homogenous parts. *For more, see the Nov 27 issue of New Electronics.