Consequently, through this agreement, joint customers will be able to obtain a complete design IP solution from Cadence, a collaborative partner in the Samsung Advanced Foundry Ecosystem (SAFE), including 112/56/25/10G PHY/MAC, PCI Express (PCIe) 6.0/5.0/4.0/3.1 PHY/Controller, Universal Chiplet Interconnect Express (UCIe) PHY/Controller, USB3.x PHY/Controller and a complete PHY and controller offering for GDDR6 and DDR5/4.
The agreement also encompasses the enablement of the latest DDR5 8400+ and GDDR7 solutions on Samsung Foundry’s advanced SF3 technology, providing a migration path for customers looking for a high-performance, high-bandwidth memory interface solution for designing generative AI/ML, hyperscale, and high-performance computing (HPC) applications.
The Cadence design IP solution delivers power, performance, and area (PPA) with feature sets that enable greater differentiation, versatility, and innovation for large-scale SoC designs. In addition, Cadence provides full subsystem delivery with integrated PHY and controller IP to simplify integration, minimise risks, and enable faster time to market.
“Through this new multi-year IP expansion plan, we’ll further solidify our commitment to empowering joint customers with access to a complete design IP portfolio on SF5A technology as well as the leading DDR5 8400+ and GDDR7/6 solutions on SF3,” said Jongshin Shin, EVP of Samsung Foundry and Head of IP Ecosystem.
“We can deliver a rich set of high-performance IP with competitive PPA that meets the most demanding requirements for HPC, AI/ML, networking, storage, and automotive applications. Developing the latest GDDR7 IP on SF3 demonstrates our leadership in this market segment,” added Rishi Chugh, vice president of product marketing in the IP Group at Cadence.
