Designed to the latest state-of-the-art interface standards, the Design IP portfolio enables customers to develop advanced SoCs for more demanding applications, including high-performance computing (HPC), artificial intelligence/machine learning (AI/ML), networking, storage, and automotive.
The IP portfolio from Cadence in TSMC’s N5 process includes 112/56/25/10 Gbps Ethernet PHY/MAC, PCIe 6.0/5.0/4.0/3.1 PHY/Controller, 40Gbps UltralinkTM D2D PHY, and complete PHY/Controller for GDDR6, DDR5/4, and LPDDR5/4x.
This Design IP is able to deliver optimal power, performance and area (PPA) together with rich feature sets to enable much greater differentiation, versatility and innovation when it comes to large-scale SoC designs.
In addition, Cadence is providing full subsystem deliveries with integrated PHY and controller IP to simplify integration, minimise risks, and enable faster time to market.
“TSMC worked closely with Cadence, our long-standing ecosystem partner, to enable leading-edge designs, which deliver significant power, performance and area improvements on our advanced technologies,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “The strong collaboration between Cadence’s Design IP and TSMC’s IP9000 teams promotes high-quality IP delivery to help our mutual customers achieve first-pass silicon success and faster time-to-market.
"Cadence has collaborated with TSMC for decades to provide high-quality silicon-proven IP on advanced process nodes to meet the most demanding requirements for HPC, AI/ML, networking, storage, and automotive applications;” said Rishi Chugh, vice president of Design IP Product Management at Cadence. "The wide adoption of our Design IP in TSMC’s N5 process demonstrates the excellence and quality of Cadence’s Design IP, which is empowering customers to design highly differentiated product solutions.”
