The company said that it has optimised power, performance and area (PPA) results across a variety of application areas including automotive, mobile, networking, high-performance computing and artificial intelligence (AI).
The flow, which has been used in hundreds of completed advanced-node tapeouts, now features multiple industry-first capabilities including unified placement and physical optimisation engines plus machine learning (ML) capabilities, enabling design excellence with up to 3X faster throughput and up to 20% improved PPA.
• Cadence digital full flow’s iSpatial technology: The iSpatial technology integrates the Innovus Implementation System’s GigaPlace Placement Engine and the GigaOpt Optimizer into the Genus Synthesis Solution, providing techniques such as layer assignment, useful clock skew and via pillars. The iSpatial technology also allows a seamless transition from Genus physical synthesis to Innovus implementation using a common user interface and database.
• ML capabilities: ML capabilities allows users to leverage their existing designs to train the iSpatial optimisation technology to reduce design margins versus traditional place and route flows.
• Optimal signoff convergence: The digital full flow incorporates unified implementation, timing- and IR-signoff engines, offering enhanced signoff convergence by concurrently closing the design for all physical, timing and reliability targets. This allows customers to reduce design margins and iterations.
“The new digital full flow enhancements build upon the widely adopted integrated flow, further advancing Cadence’s digital and signoff design capabilities and enabling customers to achieve SoC design excellence,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence.
“We’ve collaborated closely with our customers who are under pressure to meet compressed schedules with increasingly large designs, offering them the features they need to realise PPA gains more efficiently.”
