The test chip – a 64bit CPU (shown below) – was created using a custom 3nm standard cell library and a TRIM metal flow, in which the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.
“As process dimensions reduce to the 3nm node,” said An Steegen, pictured, executive vice president for semiconductor technology and systems at imec, “interconnect variation becomes much more significant. Our work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated.”
Cadence’s Innovus System is a massively parallel physical implementation system that enables engineers to deliver designs with optimal power, performance and area targets to market quickly. Genus is a high-capacity RTL synthesis and physical synthesis engine that addresses the latest FinFET process node requirements.
“Imec’s state-of-the-art infrastructure enables pre-production innovations ahead of industry demands, making them a critical partner for us in the EDA industry,” said Dr Chin-Chi Teng, general manager of Cadence’s Digital and Signoff Group. “Expanding upon the work we did with imec in 2015 on the industry’s first 5nm tapeout, we are achieving new milestones with this new 3nm tapeout, which can transform the future of mobile designs at advanced nodes.”
For the project, EUV and 193 immersion lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions.