The partners say they optimised design rules, libraries and place and route technology to obtain optimal power, performance and area scaling using Cadence’s Innovus Implementation System.
“Our collaboration with Cadence plays an important part in the development of the world’s most advanced geometries, including 5nm and below,” said An Steegen, imec’s senior vice president of process technology.
The test chip, based on a processor design, not only used EUV lithography. but also self-aligned quadruple patterning at 193nm. In the latter process, metal pitches were scaled to 24nm in order to push the limit of patterning.
“By achieving this milestone, Cadence and imec continue to demonstrate our dedication toward pushing patterning technologies to increasingly smaller nodes,” said Dr Anirudh Devgan, general manager of Cadence’s Digital and Signoff Group.
