Cadence said that it would work with the Alliance to help advance the adoption of Intel process and packaging technologies as well as its own state-of-the-art digital, custom/analogue, verification and advanced IC packaging EDA solutions, along with Cadence Design, Verification and Tensilica IP.
Over the past few days a number of companies have announced that they will be joining the Alliance. The benefits to Cadence will be that it will have early access to process and advanced IC packaging roadmaps, process design kits (PDKs) and technical training. This will allow Cadence R&D teams to fine-tune EDA tools and IP for the Intel portfolio of process and packaging technologies so customers can meet power, performance and area (PPA) requirements.
“We’re collaborating with world-leading partners like Cadence to ensure our customers have access to a robust, comprehensive design ecosystem, process technologies, advanced packaging technologies and manufacturing capabilities,” said Dr. Randhir Thakur, president of IFS. “Cadence is constantly developing new solutions and IP to stay in front of customer demands, making them a critical ecosystem partner that aligns with our mission to address the growing global demand for chips with breakthrough SoC design technologies.”
“By joining the IFS Ecosystem Alliance, we’re demonstrating our commitment to ensuring that customers can quickly become proficient using Cadence solutions and IP supporting Intel process and packaging technologies,” explained Dr. Anirudh Devgan, president and CEO of Cadence. “Our customers are under extreme pressure to deliver power-efficient and performance-optimized SoCs, and the Cadence and IFS collaboration lets our customers innovate with confidence.”
