This solution provides users with actionable intelligence to accelerate the register transfer level (RTL) design and implementation process.
Front-end designers can access digital design analysis and debugging capabilities from a single, unified cockpit, enabling fully optimised RTL design prior to implementation handoff. As a result, users will also be able to leverage generative AI for RTL design exploration and big data analytics using Cadence’s AI portfolio.
Using the Joules RTL Design Studio, users can achieve physical estimates quickly and accurately, unlocking up to 5X productivity and up to 25% quality of results (QoR) improvements in the RTL, according to Cadence.
The studio expands upon Cadence’s existing Joules RTL Power Solution, addressing all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC). In addition, the new tool comes with a host of productivity-enhancing features and benefits, including:
- Intelligent RTL debugging assistant system: Provides early PPAC metrics as well as actionable debugging information throughout the design cycle - logical, physical, and production implementation - so engineers can explore “what-if” scenarios and potential resolutions to minimise iterations and improve design outcomes.
- Based on proven engines: Joules RTL Design Studio shares the same engines as the Innovus Implementation System, Genus Synthesis Solution, and Joules RTL Power Solution, enabling users to access all analysis and design exploration features from a single GUI for optimal QoR.
- Powerful AI integrations: Joules RTL Design Studio has an integration with the generative-AI solution, Cadence Cerebrus Intelligent Chip Explorer, to explore design space scenarios, such as floorplan optimisation and frequency versus voltage trade-offs. Additionally, the Cadence Joint Enterprise Data and AI (JedAI) Platform allows trend and insight analysis across different versions of the RTL or across previous project generations.
- Lint checker integration: Allows engineers to run lint checkers incrementally to rule out data and setup issues up-front, reducing errors and time to completion.
- Unified cockpit: Provides RTL designers with an efficient, user-friendly experience, offering physical design feedback, localisation and categorisation of violations, bottleneck analysis and cross-probing between RTL, schematic, and layout.
“Now RTL designers can rapidly access all the physical information needed for PPAC debug without having to wait for implementation, which previously took days or weeks,” said Dr. Chin-Chi Teng, senior VP and general manager of the Digital & Signoff Group at Cadence. “Joules RTL Design Studio gives designers visibility into the challenges when they can still be addressed easily, ultimately speeding time to market. Our early engagements reaffirmed our initial target of up to 5X faster RTL convergence and up to 25% improved QoR.”
