The IP consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications helping customers to design extremely power-efficient SoCs with accelerated time to market.
The Cadence IP offers a highly power-efficient implementation of the standard, with several evaluations from leading customers indicating it provides industry best-in-class power at the maximum data transfer rate of 32GT/s and worst-case insertion loss.
Leveraging Cadence’s existing N7/N6 silicon validated offering, the N5 design provides a full 512GT/s (gigatransfers per second) power-optimised solution across the full range of operating conditions with a single clock lane.
In conjunction with Cadence’s low-latency Controller IP for Compute Express Link (CXL), the Cadence PHY IP enables a new class of applications for cache-coherent interconnects for processors, workload accelerators and memory expanders, as well as support for a wide range of Ethernet protocols. This provides flexible use cases for systems that need to leverage the same IP for the networking class of applications.
“Increasingly, our customers are demanding not just point IP, but total solutions that provide an edge by shortening development timeline and accelerating end-product deployment. The addition of the ultra-low power PCIe 5.0 solution to our portfolio of high-performance IP on the TSMC N7/N6, N5 and N3 technologies fulfills this need,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “Our close collaboration with TSMC ensures that we can continue to develop advanced IP on TSMC’s most advanced processes."
“As a long-standing PCI-SIG member, Cadence has played a role in promoting the adoption of PCIe technology,” said Al Yanes, president and chairman of PCI-SIG. “With its continued investment and innovation in PCIe IP, Cadence is one of the member companies enabling the latest standards to be available for widespread deployment.”
