PCS-SIG was the industry’s first event for PCIe 5.0 specification compliance and was held in April.
The solutions were tested to their full potential and complied with the full speed of 32GT/s for PCIe 5.0 technology. The compliance programme provides designers with testing procedures to assess that the PCIe 5.0 interfaces on their system-on-chip (SoC) designs will operate as expected.
The Cadence IP for PCIe 5.0 technology consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high bandwidth hyperscale computing, networking and storage applications. With Cadence’s PHY and Controller Subsystem for PCIe 5.0 architecture, customers will be able to design extremely power-efficient SoCs while accelerating time to market.
“We are pleased Cadence has certified its comprehensive IP family for compliance with the PCIe 5.0 protocol on TSMC’s advanced processes,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “Our continued close collaboration with Cadence is helping our mutual customers meet the stringent power and performance requirements and accelerate silicon innovation with leading-edge design solutions benefiting from TSMC’s advanced technologies.”
“With the lowest power consumption in the market as validated by our customers, Cadence’s certified PHY and Controller IP for PCIe 5.0 enables them to develop extremely power-efficient SoCs,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “With our multi-lane subsystem-on-a-chip solution, our customers can see IP compliance being achieved in form factors that match their target applications.”
“As a long-standing PCI-SIG member, Cadence plays a role in the advancement of PCIe technology,” explained Al Yanes, President and Chairperson of PCI-SIG. “By participating in the compliance programme, Cadence is helping to further the continued adoption of the PCIe architecture.”
