At the recent DATE conference in Grenoble, Carlo Reita, director of nanoelectronics technical marketing and strategy with CEA-Leti, said the Institute sees FD-SOI providing a path via 14nm and 10nm nodes to an approach for 7nm that is also likely to be adopted as the follow on to FinFET processes.
"We believe that, at less than 10nm, both planar and FinFET will have to converge on nanowire. The core processes we use for planar can be used for nanowires," Reita claimed.
In common with Intel, which has suggested that the 7nm node and possible successors will need to use III-V semiconductors, Reita said: "We are also starting to include new materials for the nanowires."
"We are working on 14nm with ST and are beginning to concentrate on 10nm FD-SOI. We already have preliminary results that show it's scalable to 10nm," Reita added.
At 10nm, the contacted poly pitch, which determines effective transistor density, will be reduced from 90nm in the 14nm process to 64nm. But the main change will be a reversal of the gate-deposition process, which for 28nm and 14nm, will be gate-first – generally considered to be a cheaper approach to building planar high-k metal-gate structures.
"We will move to gate-last. We expect that it will be a cheaper process than what is being done for other technologies, even when the cost of the substrate is taken into account," Reita claimed.
CEA-Leti also plans to offer monolithic integration as another way of increasing die density using a approach dubbed CoolCube that could potentially integrate combine FinFET with FD-SOI, with each on a different layer. "We are currently working on 28nm and 14nm nodes and collaborating with companies like Qualcomm, IBM and ST. It will be a big breakthrough if we can solve some technology challenges that are still open."
To support MCUs and similar highly embedded designs, CEA-Leti and GlobalFoundries, which has a licence, along with Samsung, to fab FD-SOI products, are developing non volatile memory modules. But this will entail a shift from flash.
Reita explained: "We decided some time ago there was no way to put [charge] trap-storage memories into 28nm. So we are working on resistive RAM and magnetic RAM. We are looking at all three types of resistive RAM before making a final choice."
Gerd Teepe, GlobalFoundries' director of design enablement, said the company's focus is on magnetic RAM for a 28nm compatible non volatile memory.
Although CEA and ST are working on an enhanced RF variant process that will take Fmax to 350GHz, Olivier Thomas, CEA-Leti design centre project leader, said a paper describing a reconfigurable 60GHz power amplifier at the recent ISSCC event showed that high speed RF designs are already feasible using the existing process. "There is a sweet spot for FD-SOI in millimetre wave designs", Thomas claimed.
Design work to further reduce the power consumption of FD-SOI is continuing by exploiting the combination of near threshold operation with dynamic body biasing. Thomas said this will push the viable operating voltage for FD-SOI down to around 0.5V. Experiments with circuits operating down to 0.6V have already demonstrated the ability to support low leakage and then boost performance for gigahertz speeds, although there is today limited automated EDA tool support for the technique.
