This initiative aligns with the ambition of the EU Chips Act, which seeks to bolster EU semiconductor capabilities and ensure technological sovereignty.
The pilot line will develop five new sets of technologies:
- FD-SOI (with two new generation nodes at 10nm and 7nm),
- Several types of embedded non-volatile memories (OxRAM, FeRAM, MRAM and FeFETs),
- Radio-frequency components (switches, filters and capacitors),
- Two 3D integration options (heterogeneous integration and sequential integration), and
- Small inductors to develop DC-DC converters for Power Management Integrated Circuits (PMIC).
Invented by CEA-Leti, FD-SOI is a planar CMOS technology that offers PPAC-E (Performance, Power, Area, Cost and Environmental impact) for mixed circuits (mixing digital, analogue and radio-frequency blocks). FD-SOI has been increasingly adopted by global semiconductor companies due to its tight electrostatic control at the transistor level and because it is well suited for highly innovative power-management technologies.
The boom in the FD-SOI market is therefore anticipating the 10nm and 7nm next-generation nodes.
No less than 43 companies throughout the electronic-systems value chain, from materials providers and equipment manufacturers to fabless companies, EDAs, IDMs, system houses and end-users from ITC, automotive, medical device or space and security markets, have formally expressed their support for the FAMES initiative, underlying the creation of an ecosystem of start-ups, SMEs and industry leaders.
“By integrating and combining a set of cutting-edge technologies, the FAMES Pilot Line will open the door to disruptive system-on-chip architectures and provide smarter, greener and more efficient solutions for future chips. The FAMES project will indeed pay special attention to semiconductor sustainability challenges,” said Jean-René Lèquepeys, CTO of CEA-Leti.
"This pilot line will advance essential semiconductor technologies, while maintaining a strong focus on sustainability, and foster the collaboration between several European actors. The Chips Joint Undertaking (Chips JU) aims to act as a catalyst and a model for further public and private collaborations in key areas,” explained Jari Kinaret, the Chips JU executive director.
The FAMES Consortium brings together a number of partners: the pilot line coordinator, CEA-Leti (France), imec (Belgium), Fraunhofer Mikroelektronik (Germany), Tyndall (Ireland), VTT (Finland), CEZAMAT WUT (Poland), UCLouvain (Belgium), Silicon Austria Labs (Austria), SiNANO Institute (France), Grenoble INP-UGA (France) and the University of Granada (Spain).
The five new technologies will create market opportunities for low-power microcontrollers (MCU), multi-processor units (MPU), cutting-edge AI and machine learning devices, smart data-fusion processors, RF devices, chips for 5G/6G, chips for automotive markets, smart sensors and imagers, trusted chips and new space components.
The pilot line will be accessible to all EU stakeholders (universities, RTOs, SMEs and industrial companies) and countries through annual open calls and upon request, following a fair and non-discriminatory selection process.
The project will benefit from funding that will be provided in equal parts by participating member states and the Chips JU.
