Configurable cores added to design service offering

The cores are based on EnSilica's eSi-RISC scalable processor architecture, which supports 16 and 32bit configurations. According to the company, the cores have been silicon proven over a number of asic and fpga designs. With selectable Harvard/von Neumann memory and configurable cache options, their pipelined nature is said to provide a technology independent solution suited to fpga applications, but which can be migrated between different fpgas or to asics. "Several business requirements drove us to enhance our design services capability with the development of these new cores," said EnSilica managing director Ian Lankshear, pictured. "We wanted a single architecture that would be scalable over a range of embedded applications, enabling customers to secure their software investment while addressing a range of needs. A high level of configurability would also enable hardware resources to be optimised to customers' applications, minimising area and power to a level not possible with a general purpose processor architecture." The 16bit eSi-1600 processor uses 8.5k gates, delivers up to 0.7DMIPS/MHz and consumes 15µW/MHz in a 0.13µm technology. The eSi-3200 is a 32bit core designed for use with on chip memory. Requiring 15k gates, the core's five stage pipeline can achieve 700MHz in a 90nm process, delivering up to 0.9DMIPS/MHz. Meanwhile, the eSi-3250 is optimised for use with off chip memory and features configurable instruction and data caches (up to 64kbyte direct mapped or two or four way associative). Delivering up to 1.2DMIPS/MHz, the core has an optional IEEE754 floating point unit and MMU. "The eSi-RISC processor cores will give our design services an additional edge in the market," Lankshear continued. "Our expertise in communications and multimedia will allow us to optimise the cores and add the required instructions to maximise their performance enabling some interesting ultra low power applications."