Cortus launches new processor cores, instruction set
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Processor IP developer Cortus has launched new cores– the APS23 and 25 – based on its V2 instruction set. The V2 instruction set extends functionality by adding 24bit instructions to the existing 16 and 32bit instructions. Roddy Urquhart, pictured, vp of marketing, noted: "This instruction set will provide for better code density. The different way of coding will be more efficient and we are seeing a 16% improvement in code density."
The APS23 core is said to deliver a new level of efficiency, along with ease of integration, for low power connected devices. The core reduces system power by optimising instruction memory size. Meanwhile, the APS25 core is aimed at embedded systems with more computational requirements, as well as greater code density and extendibility.
Urquhart said: "The APS23 will be suitable for many applications which need a power efficient core. The APS25 can also be integrated into more complex subsystems and there is the ability to extend the instruction set with a coprocessor interface."
The APS23 has a Harvard architecture, 16 32bit registers, a three stage pipeline and a sequential multiplier. It delivers 1.44 CoreMarks/MHz in computational performance and draws a maximum of 12.2µW/MHz.
The APS25 is similar to the APS23, but has a five stage pipeline. Users can expect a performance of up to 2.09CoreMarks/MHz, with a maximum power consumption of 20.8 µW/MHz.
Both cores are synthesisable and will be available as RTL. Urquhart said Cortus' V1 cores have been manufactured on processes ranging from 28nm to 0.35µm.
